參數(shù)資料
型號(hào): ML60852A
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁(yè)數(shù): 17/82頁(yè)
文件大小: 370K
代理商: ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
23/81
(6) SOF Interrupt
Operation
Source of operation
Description (conditions, responses, etc.)
SOF Interrupt generation
ML60852A
When SOF interrupt has been enalbed (bit D0 of
INTENBL2), and an SOF packet is detected on the USB
bus.
End of SOF interrupt
Local MCU (firmware)
When a “1” is written in the SOF interrupt status bit of the
interrupt status register 2 (bit D2 of INTSTAT2).
(7) USB Bus reset assert interrupt
Operation
Source of operation
Description (conditions, responses, etc.)
USB Bus reset assert
interrupt generation
ML60852A
The ML60852A automatically detects the condition when
the SE0 state continues for 2.5s or longer at the D+ and
D- pins. Once this condition is detected, if USB bus reset
assert interrupt has been enabled (D1 of INTENBL2) an
interrupt is generated.
→ Carry this out by firmware processing for bus reset.
End of USB bus reset assert
interrupt
Local MCU (firmware)
When a “1” is written in the corresponding bit of the
interrupt status register 2 (D1 of INTSTAT2).
(8) USB Bus reset de-assert interrupt
Operation
Source of operation
Description (conditions, responses, etc.)
USB Bus reset de-assert
interrupt generation
ML60852A
When USB Bus reset de-assert interrupt enable bit (D2 of
INTENBL2) has been enalbed and there is a recovery to
the J state from the SE0 state of 2.5s or longer at the D+
and D- pins.
→ Carry this out by firmware processing for bus reset
release.
End of USB bus reset
de-assert
Local MCU (firmware)
When a “1” is written in the corresponding bit of the
interrupt status register 2 (D2 of INTSTAT2).
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參數(shù)描述
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