參數(shù)資料
型號: ML60852A
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 51/82頁
文件大?。?/td> 370K
代理商: ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
54/81
EP1, 2, 3, 4, 5 Control Registers (EP1, 2, 3, 4, 5CONT)
Address
0 x 49 to 4D
Type
Bit map
Access type
See below
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
0
Stall bit:
During EP0 reception (data stage of a control write transfer), if a packet with a number
of bytes exceeding the maximum packet size specified in EP0PLD is received (or if the
EOP packet is missing), the ML60852A automatically sets this bit to “1”.
Data sequence toggle bit: A reset will be made when a “1” is written in this bit. At the time of initializing the EP,
reset the toggle bit of the data packet by writing a “1” to this bit, and specify PID of
DATA0 (this bit too will become “0”). Thereafter, the synchronization operation using
the data sequence toggle mechanism will be made automatically.
FIFO Clear:
The EP will be valid only when it has been set for transmission by the EP control register.
When a “1” is written in this bit, the transmit FIFO of that EP will be cleared. (However,
this bit itself will remain “0”.)
Rate feedback:
This bit is valid only in the case of EP3. This bit will be fixed at “0” in all other EPs.
Stall bit
(R/W)
Data sequence toggle bit
(R/Reset)
FIFO Clear (R/Reset)
Rate feedback (R/W)
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參數(shù)描述
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