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參數資料
| 型號： | ML60852A |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 53/82頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
56/81
EP3 Payload Register (EP3PLD)
Address
0 x 53
Type
6-Bit data
Access type
Read/Write
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
0
Maximum packet size: Make the local MCU write in this register the value of the descriptor wMaxPacketSize of
the end point selected by the Set_Configuration request from the host. The size of all
packets other than a short packet is specified here in units of a byte. Set 20h (32 bytes) or
less because the FIFO size is 32 bytes.
When EP3 has been assigned for reception, if a data packet with a number of bytes
exceeding the maximum packet size specified in this register is received, the receive
packet ready status bit is not asserted, but the stall bit is set in EOP and the stall handshake
is returned to the host.
There is no need to use this register when EP3 has been assigned for transmission.
EP4, 5 Payload LSB Registers (EP4, 5PLDLSB)
Address
0 x 54, 55
Type
10-Bit or 9-bit data
Access type
Read/Write
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
Maximum packet size LSB (R/W)
Maximum packet size LSB: Make the local MCU write in this register the value of the descriptor wMaxPacketSize
of the end point selected by the Set_Configuration request from the host. The lower 8
bits should be stored in this register and the higher-order bytes should be written in the
EP4,5 payload registers MSB. The maximum packet size is specified in units of a
byte.
When the EP has been assigned for reception, if a data packet with a number of bytes
exceeding the maximum packet size specified in these registers is received, the receive
packet ready status bit is not asserted, but the stall bit is set in EOP and the stall
handshake is returned to the host.
On the other hand, when the EP has been assigned for transmission, the transmit
packet ready bit is set automatically when writing by the DMA controller of data with
the maximum packet size specified in this register is completed.
Maximum packet size
(R/W)
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相關代理商/技術參數 |
參數描述 |
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| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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