參數(shù)資料
型號: ML60852A
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 30/82頁
文件大?。?/td> 370K
代理商: ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
35/81
EP3 FIFO (EP3FIFO)
Address
0 x 7B
Type
Byte data
Access type
Write only
or
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
xxxx
xx
After a bus reset
x
xxxx
xx
Definition
EP3 Transmit data or EP3 receive data
It is possible to specify the direction of transfer of EP3 by setting the EP3 configuration register EP3CONF. The
FIFO address of EP3 is the same in both the transmit direction and the receive direction.
When EP3CONF (D7) = 0, EP3 is in the receive direction and EP3FIFO is in the read-only state.
When EP3CONF (D7) = 1, EP3 is in the transmit direction and EP3FIFO is in the write-only state.
When set for transmission, all bytes of EP3FIFO can be cleared by clearing EP3FIFO (writing a “1” into EP3CONT
(D2)).
EP4 FIFO (EP4FIFO)
Address
0 x 7C
Type
Byte data
Access type
Write only
or
Read only
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
x
xxxx
xx
After a bus reset
x
xxxx
xx
Definition
EP4 Transmit data or EP4 receive data
It is possible to specify the direction of transfer of EP4 by setting the EP4 configuration register EP4CONF. The
FIFO address of EP4 is the same in both the transmit direction and the receive direction.
When EP4CONF (D7) = 0, EP4 is in the receive direction and EP4FIFO is in the read-only state.
When EP4CONF (D7) = 1, EP4 is in the transmit direction and EP4FIFO is in the write-only state.
When set for transmission, all bytes of EP4FIFO can be cleared by clearing EP4FIFO (writing a “1” into EP4CONT
(D2)).
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