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參數(shù)資料
| 型號： | ML60852A |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 57/82頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
59/81
EP0 Status Register (EP0STAT)
Address
0 x 60
Type
Bit map
Access type
See below
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
0
Please note the R/Reset and R/Set notation used above. R/Reset means: the bit field can be
read by the local MCU/and it is Reset (to ‘0’) when a “1” is written to it. The R/Set means: the
bit field can be read by the local MCU/and it is Set (to ‘1’) when a 1 is written to it.
Setup ready:
This bit is set automatically when a setup packet normally arrives in the 8-byte setup register,
and the EP0 Receive FIFO is locked.
If INTENBL1(0) is asserted, the
INTR pin is also asserted automatically when this bit is set.
The local MCU should write a “1” into this bit after reading out the 8-byte setup data.
When this is performed, the setup ready bit is reset and the
INTR pin also is de-asserted.
During a control write transfer, the packet ready bit of EP0 is reset simultaneously and the
lock condition is released, and it becomes possible to receive packets by EP0 during the data
stage. The register will not change even if a “0” is written in this bit.
EP0 transmit packet
ready bit (D1):
The local MCU can read this bit. Writing when D1=1 sets this bit to “1”. The asserting and
de-asserting conditions are described below.
Bit name
Asserting condition
Operation when asserted
EP0 transmit packet ready (D1)
When the local MCU has set this bit
Data can be transmitted from EP0.
Bit name
De-asserting condition
Operation when de-asserted
EP0 transmit packet ready (D1)
1. When an ACK is received from the
host for data transmission
2. When a setup packet is received
EP0 is locked. That is, an NAK is
automatically returned when an IN
token is sent from the host.
EP0 receive packet
ready (R/Reset)
EP0 stage (R)
00 = Default state
01 = Data stage
10 = Data stage completed state
EP0 transmit packet ready
(R/Set)
Setup ready
(R/Reset)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Series Positive Voltage Detector |
| ML61_09 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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