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參數(shù)資料
| 型號： | ML60852A |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 60/82頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ML60852A |
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FEDL60852A-03
1Semiconductor
ML60852A
62/81
EP1, 2, 4, 5 Status Registers (EP1, 2, 4, 5STAT)
Address
0 x 61, 62, 64, 65
Type
Bit map
Access type
See below
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
0000
00
After a bus reset
0
0000
00
Definition
00
0000
This register is valid only when the corresponding EP has been set for bulk or interrupt transfer.
EP1,2,4,5 Receive packet ready bit (D0): This bit can be read by the local MCU. Also, this bit can be made “0” by
writing a “1” into bit D0. The asserting and de-asserting conditions of
this bit are as given below. The FIFOs of EP1, EP2, EP4, and EP5 have
a 2-layer structure and also there are independent packet ready bits for
layer A and layer B. The switching between these two layers is done
automatically by the ML60852A.
Bit name
Asserting condition
Operation when asserted
EPn Receive packet ready (D0)
When an error-free packet is received
in either layer A or layer B.
The local MCU can read the EP1
Receive FIFO. EP1 is locked in the
condition in which data packets have
been received by both layer A and
layer B.
Bit name
De-asserting condition
Operation when de-asserted
EPn Receive packet ready (D0)
When the local MCU has reset
(written a “1” in) the bits of both layer
A and layer B.
Reception can be made by EP1 when
the bit of either layer A or layer B has
been reset.
EP1,2,4,5 Transmit packet ready bit (D1): This bit can be read by the local MCU. Also, this bit can be made “1” by
writing a “1” into bit D1. The asserting and de-asserting conditions of
this bit are as given below. The FIFO of EP1 has a 2-layer structure and
also there are independent packet ready bits for layer A and layer B. The
switching between these two layers is done automatically by the
ML60852A.
Bit name
Asserting condition
Operation when asserted
EPn Transmit packet ready (D1) (1)When the local MCU has set the
bits of both layer A and layer B.
(2)When the local MCU has set the
bits of either layer A or layer B.
Transmission can be made from EP1
when either layer A or layer B has
been asserted.
Bit name
De-asserting condition
Operation when de-asserted
EPn Transmit packet ready (D1) When an ACK message is received
from the host for the data transmission
to either layer A or layer B.
EP1 is locked when transmit data has
not been prepared for both layer A
and layer B.
EP Receive packet
ready (Read/Reset)
EP Transmit packet ready
(Read/Set)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML-60-V2/80721 | 制造商:Thomas & Betts 功能描述: |
| ML61 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Series Positive Voltage Detector |
| ML61_09 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Positive Voltage Detector CMOS Low Power Consumption : Typical 1.0uA at Vin=2.0V |
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