參數(shù)資料
型號: ML60852A
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 6/82頁
文件大?。?/td> 370K
代理商: ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
13/81
(3) Endpoints and FIFOs
In the ML60852A, it is possible to select, by making appropriate setting in the SYSCON register, the 5EP mode in
which there are five end points or the 6EP mode in which there are six end points. Although the transfer mode that
can be used by EP0 is fixed, it is possible to select either the bulk transfer mode or the interrupt transfer mode for the
end points EP1, EP2, and EP3, and one of the modes of isochronous, bulk, or interrupt transfer can be selected for
EP4 and EP5. In addition, it is possible to selectively set the direction of data transfer for EP1 to EP5.
5EP Mode
6EP Mode
End
point
FIFO
Capacity
Transfer
mode
Remarks
FIFO
Capacity
Transfer
mode
Remarks
EP0
Reception 32
Transmission 32
C
Reception 32
Transmission 32
Control transfer
EP1
64x2
B/Int
(IN/OUT)
DMA
Possible
64x2
B/Int
(IN/OUT)
DMA
Possible
EP2
64x2
B/Int
(IN/OUT)
DMA
Possible
64x2
B/Int
(IN/OUT)
DMA
Possible
EP3
32
B/Int
(IN/OUT)
Rate
32
B/Int
(IN/OUT)
Rate
EP4
512x2
(64x2)
Iso/B/Int
(IN/OUT)
DMA
Possible
256x2 (64x2)
Iso/B/Int
(IN/OUT)
DMA
Possible
EP5
256x2 (64x2)
Iso/B/Int
(IN/OUT)
DMA
Possible
FIFO Capacity: The unit is bytes.
Note:
Transfer modes:
C = Control transfer
B = Bulk transfer
Int = Interrupt transfer
Iso = Isochronous transfer
Rate = Compatible with data sequence toggling of rate feedback.
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