參數(shù)資料
型號： ML60852A
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 20/82頁
文件大?。?/td> 370K
代理商： ML60852A
FEDL60852A-03
1Semiconductor
ML60852A
26/81
(11) Operation of 2-layer FIFO structure during Bulk Transfer
The FIFOs of EP1 and EP2 have a 64 bytes x 2-layer structure. Also, when EP4 is assigned for bulk transfer, its
FIFO also has a 64-bytes x 2-layer structure. As a consequence, these FIFOs can temporarily store a maximum of
128 bytes of bulk transfer data. Please note that the double layered FIFO operation can be modified by changing the
settings in the transmit packet ready control register (TXPKTCONT).
(1) 2-Layer reception (bulk-out) operation (“O” indicates the assert (set to ‘1’) condition and “x” indicates de-
assert (set to ‘0’) condition)
In the case of 1
→2→3→4→5a→6
In the case of 1
→2→3→4→5b→6
Layer A
64 bytes
Layer B
64 bytes
Layer A
PKT
RDY
Layer B
PKT
RDY
EPn
receive
PKT
RDY
INTR
1
Start storing data in layer A FIFO
x
2
Data of one packet has been stored.
x
3
Start reception and storing of data in
layer B.
x
4
Local MCU starts reading layer A.
x
5a
When the storing of packet in layer B is
completed before the completion of
reading layer A.
5b
When the reading of packet in layer A is
completed before the completion of
storing data in layer B.
xxx
x
6
From 5a: Layer A has become empty.
From 5b: Layer B has become full.
x
7
Start reading layer B.
x
Note: The above illustration assumes that the local MCU (firmware) resets the receive packet ready bit of the
respective EPnSTAT register immediately after completition of reading the received data in the
corresponding endpoint’s FIFO (EPnFIFO).
When one packet of receive data is stored in layer A of the FIFO and EOP is received, the ML60852A asserts the
packet ready bit of EPn and also asserts the
INTR pin. This makes it possible for the local MCU to read the
receive data.
Subsequently, data can be received from the host, and the ML60852A switches the FIFO for storing to layer B.
When one packet of data described above has been read from layer A of the FIFO, make the local MCU reset the
receive packet ready status of EPn (by writing a “1” into bit D0 of EPnSTAT).
At the time the EPn receive packet ready status is reset, if the reception of layer B has not been completed, the
ML60852A resets the EPn receive packet ready status and de-asserts the
INTR pin.
However, if the reception of layer B has been completed a the time the EPn receive packet ready status is reset,
the ML60852A rejects the request from the local MCU to reset the EPn receive packet ready status, and
continues to maintain the EPn receive packet ready status and the asserted condition of the
INTR pin.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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