參數(shù)資料
型號： M37902FJCHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 92/143頁
文件大小： 1463K
代理商： M37902FJCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
92
CLOCK GENERATING CIRCUIT
Figure 98 shows the block diagram of the clock generating circuit.
The clock generating circuit consists of the clock oscillation circuit,
PLL frequency multiplier (PLL circuit), system clock switch circuit,
peripheral devices’ clock switch circuit, clock divider, standby control
circuit, etc. As control registers for the clock generating circuit, also,
the clock control register (address BC
16
), particular function select
register 0 (address 62
16
) are provided. (See Figures 99 and 100.)
As shown in Figure 98, clocks used in the CPU, BIU, peripheral de-
vices, watchdog timer (in other words, clocks
φ
CPU
,
φ
BIU
, f
1
to f
4096
,
Wf
32
, Wf
512
) are made from system clock f
sys
. System clock f
sys
can
be selected between fX
IN
(in other words, a clock input from pin X
IN)
and f
PLL
(in other words, an output clock generated by the PLL cir-
cuit). By setting the clock
φ
1
output select bit (bit 7 of the processor
mode register 0) to “1”, also, system clock f
sys
can be output from
port pin P4
1
, as clock
φ
1
.
The PLL circuit’s operation, system clock (f
sys
) selection, and divide
ratio selection for peripheral devices’ clocks (f
1
to f
4096
) are con-
trolled by the clock control register. The following describes about
these control.
Bit 1 of the clock control register (the PLL circuit operation enable bit)
selects the PLL circuit’s operation (stopped/active). When this bit is
set to “1”, pin V
CONT
will becomes valid, and the PLL circuit will oper-
ate. At reset, the PLL circuit operation enable bit becomes “1”. (In this
case, the PLL circuit operates.) When not using the PLL circuit, be
sure to clear the PLL circuit operation enable bit to “0” (stopped). At
the
STP
instruction execution or while the flash memory parallel I/O
mode is set, the PLL circuit stops its operation, and pin V
CONT
is in-
valid, regardless of this bit 1’s status.
Bits 2 and 3 of the clock control register (the PLL multiplication ratio
select bits) select the ratio of f
PLL
/fX
IN
. The PLL multiplication ratio
must be set so that the frequency of the PLL output clock (f
PLL
) must
be in the range from 10 MHz to 26 MHz. At reset, the PLL multiplica-
tion ratio select bits become “0,1” (
2). The change of the multipli-
cation ratio must be performed while input clock fX
IN
is set as system
clock. (In this case, bit 5 of the clock control register = “0”.) After that,
be sure to wait that the operation-stabilizing time of the PLL circuit
has passed, and switch the system clock to the PLL output clock
(f
PLL
). (In other words, set bit 5 to “1”.) Note that, after reset, the PLL
multiplication ratio select bits are allowed to be changed only once.
Bit 5 of the clock control register is the system clock select bit, and
fX
IN
is selected as the system clock when bit 5 = “0”. On the other
hand, when bit 5 = “1”, the PLL output clock (f
PLL
) is selected. At re-
set, the system clock select bit becomes “0”. When selecting f
PLL
, be
sure that the PLL circuit’s operation has been stabilized properly, and
then, set the system clock select bit to “1”. Also, when the PLL circuit
operation enable bit is cleared to “0” (the PLL circuit is stopped.), the
system clock select bit will automatically be cleared to “0”. Note that
a value of “1” cannot be written to the system clock select bit while
the PLL circuit operation enable bit =“0”.
Table 15 lists the f
sys
selection.
Bits 6 and 7 of the clock control register are the peripheral devices’
clock select bits 0, 1, and these bits select the multiplication ratio of
(f
1
to f
4096
)/(f
sys
).
Table 16 lists the internal peripheral devices’ operation clock fre-
quency. At reset, these bits become “0, 0”.
Table 15. f
sys
selection
System clock select bit
(Bit 5)
0
Table 16. Internal peripheral devices’ operation clock frequency
Internal peripheral devices
’
operation clock
f
1
f
2
10 (
3)
11 (
4)
01 (
2)
System clock f
sys
Clock source
fX
IN
f
PLL
f
PLL
f
PLL
Frequency
(Note)
f(X
IN
)
f(X
IN
)
2
f(X
IN
)
3
f(X
IN
)
4
Note:
The PLL multiplication ratio must be set so that the frequency of the PLL output clock (f
PLL
) must be in the range from 10 MHz to 26 MHz.
f(X
IN
) means the frequency of the input clock from pin X
IN
(fX
IN
). After reset, the PLL multiplication ratio select bits are allowed to be
changed only once.
PLL circuit operation enable bit
(Bit 1)
1
1
PLL multiplication ratio select bits
(Bits 3, 2)
(Note)
f
sys
/16
f
sys
/64
f
sys
/512
f
sys
/4096
f
sys
/2
Peripheral devices
’
clock select bits 1, 0 (bits 7, 6)
0 1
(Note)
f
sys
f
sys
f
sys
/8
f
sys
/32
f
sys
/256
f
sys
/2048
1 0
1 1
Note:
When selecting the peripheral devices
’
clock select bits 1, 0 =
“
01
2
”
, be sure that system clock f
sys
does not exceed 13 MHz.
f
16
f
64
f
512
f
4096
f
sys
/2
f
sys
/4
f
sys
/32
f
sys
/128
f
sys
/1024
f
sys
/8192
0 0
f
sys
Do not select.
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