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參數(shù)資料
| 型號： | M37902FJCHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機 |
| 文件頁數(shù)： | 67/143頁 |
| 文件大?。?/td> | 1463K |
| 代理商： | M37902FJCHP |
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67
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CLOCK SYNCHRONOUS SERIAL COMMUNI-
CATION
A case where communication is performed between two clock syn-
chronous serial I/O ports as shown in Figure 69 will be described.
(The transmission side will be denoted by subscript j and the receiv-
ing side will be denoted by subscript k.)
Bit 0 of the UARTj transmit/receive mode register and UARTk trans-
mit/receive mode register must be set to
“
1
”
and bits 1 and 2 must be
“
0
”
. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj transmit/receive mode register of the clock send-
ing side is cleared to
“
0
”
to select the internal clock. Bit 3 of the
UARTk transmit/receive mode register of the clock receiving side is
set to
“
1
”
to select the external clock. Bits 4, 5 and 6 are ignored in
clock synchronous mode. Bit 7 must always be
“
0
”
.
The clock source is selected by bit 0 (CS
0
) and bit 1 (CS
1
) of the
clock-sending-side UARTj transmit/receive control register 0. As
shown in Figure 64, the selected clock is divided by (n+1), then by 2,
is passed through a transmission control circuit, and is output as
transmission clock CLKj. Therefore, when the selected clock is fi,
Bit Rate = f
i
/ {(n + 1)
×
2}
On the clock receiving side, the CS
0
and CS
1
bits of the UARTk
transmit/receive control register 0 are ignored because an external
clock is selected.
Both of UART0 and UART1 can use CTS and RTS functions.
Bit 4 of the UARTi transmit/receive control register 0 is used to de-
“
when
CTS or RTS signal is used. Bit 4 must be
“
1
”
when CTS and RTS sig-
RTS pin can be used as a normal port pin.
When using pin CTS/RTS, :
If bit 2 of the UARTi transmit/receive control register 0 is cleared to
“
0
”
, CTS input is selected.
If bit 2 is set to
“
1
The case using CTS and RTS signals are explained below. As
shown in Figure 76, bits 2 and 3 of the serial I/O pin control register
can determine whether port pins P8
3
and P8
7
are used as pins TxDi
or as port pins. When bits 2 and 3 are
“
0
”
, P8
3
and P8
7
function as
pins TxDi; when bits 2 and 3 are
“
1
”
, P8
3
and P8
7
function as port
pins. Therefore, in the input-only system where pins TxDi are not
used, pins TxDi can function as port pins.
Fig. 69 Clock synchronous serial communication
UARTj transmit register
TxDj
RxDj
CLKj
CTSj
UARTj transmit buffer register
UARTj receive buffer register
UARTj receive register
UARTj Transmit/Receive mode register
UARTj Transmit/Receive control
register 0
UARTj Transmit/Receive control
register 1
0
0
0
0
T
EPTY
CS
1
CS
0
RE
RI
OER
FER
PER
CPL
CPL
SUM
TI
TE
0
UARTk transmit register
UARTk transmit buffer register
UARTk receive buffer register
UARTk receive register
UARTk Transmit/Receive mode register
UARTk Transmit/Receive control
register 0
UARTk Transmit/Receive control
register 1
0
1
1
0
1
T
EPTY
MSB
/LSB
RE
RI
OER
FER
PER
SUM
TI
TE
0
1
TxDk
RxDk
CLKk
RTSk
MSB
/LSB
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