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參數(shù)資料
| 型號(hào)： | M37902FJCHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 112/143頁(yè) |
| 文件大?。?/td> | 1463K |
| 代理商： | M37902FJCHP |
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MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
112
Busy
Terminated normally.
Terminated normally.
Terminated normally.
Ready
Terminated by error.
Terminated by error.
Terminated by error.
Table 21. Bit definition of status register
SR.7 (D
7
)
SR.6 (D
6
)
SR.5 (D
5
)
SR.4 (D
4
)
SR.3 (D
3
)
SR.2 (D
2
)
SR.1 (D
1
)
SR.0 (D
0
)
Write State Machine (WSM) Status
Reserved
Erase Status
Programming Status
Block Status After Programming
Reserved
Reserved
Reserved
Symbol
Status
Definition
“1”
“0”
Write State Machine (WSM) Status Bit (SR.7)
This bit reports the operation status of the WSM. This bit is set to “1”
(READY) after the system power is turned on or after reset is re-
moved.
During the automatic programming or erase operation, this bit is
cleared to “0” (BUSY), however, set to “1” upon completion of them.
Erase Status Bit (SR.5)
This bit reports the status of the automatic erase operation. This bit
is set to “1” if an erase error occurs and returns to “0” if one of the
following conditions is satisfied:
the system power is turned on.
reset is removed.
the clear status register command (50
16
) is executed.
Programming Status Bit (SR.4)
This bit reports the status of the automatic programming operation.
This bit is set to “1” if a programming error occurs and returns to “0”
if one of the following conditions is satisfied:
the system power is turned on.
reset is removed.
the clear status register command (50
16
) is executed.
Block Status After Programming Bit (SR.3)
This bit is set to “1”, upon completion of the page programming op-
eration, if the excessive programming
(Note)
occurs. That is, the sta-
tus register becomes “80
16
” when the programming operation is
terminated normally, “90
16
” when the programming operation is
failed, and “88
16
” when the excessive programming occurs.
Under the condition that any of SR.5, SR.4 and SR.3 = “1”, none of
the page programming, block erase, erase all unlocked block, and
lock bit programming commands can be accepted. To execute these
commands, in advance, execute the clear status register command
(50
16
) to clear the status register.
Both of SR.4 and SR.5 are set to “1” under the following conditions
(Command Sequence Error):
(1) when data other than “D0
16
” and “FF
16
” is written to the data in
the 2nd bus cycle of the lock bit programming command (77
16
/
D0
16
)
(2) when data other than “D0
16
” and “FF
16
” is written to the data in
the 2nd bus cycle of the block erase command (20
16
/D0
16
)
(3) when data other than “D0
16
” and “FF
16
” is written to the data in
the 2nd bus cycle of the erase all unlocked block command
(A7
16
/D0
16
)
Note that, writing of “FF
16
” forces the microcomputer into the read
array mode. Simultaneously with this, the command written in the 1st
bus cycle will be canceled.
Note:
The excessive programming means the status that memory
cells are too depleted, so data cannot be read out correctly.
Full Status Check
The full status check reports the results of the erase or programming
operation.
Figure 120 shows the full status check flowchart and actions to be
taken if an error has occurred.
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