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| 型號(hào)： | M37902FJCHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 38/143頁(yè) |
| 文件大?。?/td> | 1463K |
| 代理商： | M37902FJCHP |
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M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38
Chip select wait controller
By the control of the chip select wait controller (CSWC), the chip se-
lect function for the maximum of 4 blocks can be set at the bus ac-
cess to the external area.
Also, by the setting of the CSWC, port pins P4
4
to P4
7
can operate
as chip select output pins (CS
0
to CS
3
).
Figure 27 shows a chip select output waveform example.
This chip select function determines the following items of the chip
select area: start address, address
’
s block size, wait number, exter-
nal data bus width, RDY control validity, burst ROM specification,
recovery cycle insertion validity, and area multiplication validity.
For the external area except for areas CS
0
to CS
3
, the processor
mode registers 0, 1 determine the above items. After reset is re-
moved, when the microcomputer starts it
’
s operation in the micropro-
cessor mode, area CS
0
is automatically selected.
Table 7 lists the function of areas CS
0
to CS
3
.
Figure 28 shows the bit configuration of the CS
0
/CS
1
/CS
2
/CS
3
con-
trol register Ls. These registers determine the following items of a
device to be connected: wait number, external data bus width (
Note:
The external data bus width of area CS
0
is determined by pin BYTE
’
s
level.), RDY control validity, burst ROM access specification, recov-
ery cycle insertion validity, and output validity of CS
0
to CS
3
.
Figure 29 shows the bit configuration of the CS
0
/CS
1
/CS
2
/CS
3
con-
trol register Hs. These registers determine block size, etc. of an ex-
ternal area to be connected. For areas CS
0
to CS
2
, by selecting
mode 1 with the area CSk setting mode select bit, an chip select area
can be set to the external area in bank 0.
Figures 30 shows the bit configuration of the area CS
0
/CS
1
/CS
2
/CS
3
start address registers. For details of these addresses
’
setting, see
Figures 31 to 33.
When area CS
i
is accessed
φ
1
A
0
to A
23
ALE
RD,
When the same area CS
i
is accessed sequentially
φ
1
A
0
to A
23
ALE
RD,
Address + 2
One access
cycle
Address
One access
cycle
Address
CS
i
BLW, BHW
BLW, BHW
One access
cycle
CS
i
Fig. 27 Chip select output waveform example
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