參數(shù)資料
型號(hào)： M37902FJCHP
廠(chǎng)商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁(yè)數(shù)： 39/143頁(yè)
文件大?。?/td> 1463K
代理商： M37902FJCHP
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39
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Bus cycle:
1
φ
+ 1
φ
1
φ
+ 2
φ
1
φ
+ 3
φ
2
φ
+ 2
φ
2
φ
+ 3
φ
2
φ
+ 4
φ
3
φ
+ 3
φ
3
φ
+ 4
φ
(Selected by bits
2, 3 at address
5E
16
and bit 0 at
address 5F
16
.)
Determined by
pin BYTE
’
s level
Valid (Selected by
bit 2 at address
5F
16
.)
Not available.
Available.
Not available.
Available.
CS
3
Banks 2
16
to FE
16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Bus cycle:
1
φ
+ 1
φ
1
φ
+ 2
φ
1
φ
+ 3
φ
2
φ
+ 2
φ
2
φ
+ 3
φ
2
φ
+ 4
φ
3
φ
+ 3
φ
3
φ
+ 4
φ
(Selected by bits
0, 1 at address
86
16
and bit 3 at
address 87
16
.)
When BYTE =
V
SS
level, 8-bit
width or 16-bit
width can be
selected arbitrary
(Note 1)
.
(Selected by bit 2
at address 86
16
.)
Valid (Selected by
bit 2 at address
5F
16
and bit 3 at
address 86
16
.)
Available.
Available.
Not available.
Available.
Bus cycle:
1
φ
+ 1
φ
1
φ
+ 2
φ
1
φ
+ 3
φ
2
φ
+ 2
φ
2
φ
+ 3
φ
2
φ
+ 4
φ
3
φ
+ 3
φ
3
φ
+ 4
φ
(Selected by bits 0, 1 at addresses
82
16
, 84
16
and bit 3 at addresses
83
16
, 85
16
.)
When BYTE = V
SS
level, 8-bit width
or 16-bit width can be selected
arbitrary
(Note 1)
. (Selected by bit 2
at addresses 82
16
, 84
16
.)
Valid (Selected by bit 2 at address
5F
16
and bit 3 at addresses 82
16
,
84
16
.)
Available.
Available.
CS
1
: Not available.
CS
2
: Available.
(Note 4)
Available.
Space where start
address can be set
Block size
Bus cycle
External data bus
width
RDY control
Burst ROM access
(Notes 2, 3)
Recovery cycle
insertion
Area multiplexed bus
access
(Note 3)
Address output
selection
(Note 5)
Bus cycle:
1
φ
+ 1
φ
1
φ
+ 2
φ
1
φ
+ 3
φ
2
φ
+ 2
φ
2
φ
+ 3
φ
2
φ
+ 4
φ
3
φ
+ 3
φ
3
φ
+ 4
φ
(Selected by bits 0, 1 at address
80
16
and bit 3 at address 81
16
.)
Determined by pin BYTE
’
s level.
Valid (Selected by bit 2 at address
5F
16
and bit 3 at address 80
16
.)
Available.
Available.
Not available.
Available.
CS
0
Mode 0
Banks 2
16
to FE
16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Mode 1
Bank 0
16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
CS
1
, CS
2
Mode 0
Banks 2
16
to FE
16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Mode 1
Bank 0
16
4 Kbytes
or 8 Kbytes
External area except
for CS
0
to CS
3
Table 7. Function of areas CS
0
to CS
3
Notes 1:
When BYTE = Vcc level, the external data bus width is fixed to 8 bits.
2:
Burst ROM access is valid only when the external data bus width is 16 bits at instruction prefetch.
3:
Burst ROM access and area multiplexed bus access cannot be used at the same time.
4:
Valid only when area CS
2
is accessed with the 8-bit external data bus width.
5:
Selected by the address output select bit (bit 4 at address 63
16
). The address output selection for each area is not available.
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