參數(shù)資料
型號： M37902FJCHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機
文件頁數(shù)： 40/143頁
文件大?。?/td> 1463K
代理商： M37902FJCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
40
Fig. 28 Bit configuration of CS
0
/CS
1
/CS
2
/CS
3
control register Ls
7
6
5
4
3
2
1
0
CS
0
control register L
External data bus width select bit
(Note 1)
0 : 16-bit width
1 : 8-bit width
RDY control bit
(Note 2)
0 : RDY control is valid.
1 : RDY control is invalid.
Area CS
0
bus cycle select bit 0
See Figure 18.
Address
80
16
At reset
42
16
Burst ROM access select bit
(Note 3)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
0 : No recovery cycle is inserted at access to area CS
0
.
1 : Recovery cycle is inserted at access to area CS
0
.
CS
0
output select bit
(Notes 4, 5)
0 : CS
0
output is disabled. (P4
4
functions as a programmble I/O port pin.)
1 : CS
0
output is enabled. (P4
4
functions as pin CS
0
.)
Notes 1:
While V
SS
level voltage is applied to pin BYTE, this bit
’
s state is cleared to
“
0
”
at reset. While V
CC
level voltage is
applied to pin BYTE, on the other hand, this bit
’
s state is set to
“
1
”
at reset.
2:
This bit is valid when the RDY input select bit (bit 2 at address 5F
16
) =
“
1
”
.
3:
While V
CC
level voltage is applied to pin BYTE, the normal access is selected regardless of this bit
’
s contents.
4:
In the single-chip mode, this bit
’
s contents are invalid. (CS
0
output is disabled.)
5:
While V
SS
level voltage is applied to pin MD0, this bit
’
s state is cleared to
“
0
”
at reset. While V
CC
level voltage is
applied to pin MD0, on the other hand, this bit
’
s state is set to
“
1
”
at reset. (Fixed to
“
1
”
.)
7
6
5
4
3
2
1
0
CS
1
control register L
CS
2
control register L
CS
3
control register L
External data bus width select bit
0 : 16-bit width
1 : 8-bit width
(Note 1)
RDY control bit
(Note 2)
0 : RDY control is valid.
1 : RDY control is invalid.
Area CS
j
bus cycle select bit 0 (j = 1 to 3)
See Figure 18.
“
0
”
at reading.
Address
82
16
84
16
86
16
At reset
42
16
42
16
42
16
Burst ROM access select bit
(Note 3)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
0 : No recovery cycle is inserted at access to area CS
j
.
1 : Recovery cycle is inserted at access to area CS
j
.
CS
j
output select bit (j = 1 to 3)
(Note 4)
0 : CS
j
output is disabled. (P4
5
to P4
7
function as programmable I/O port pins.)
1 : CS
j
output is enabled. (P4
5
to P4
7
function as pin CS
j
.)
Notes 1:
While V
CC
level voltage is applied to pin BYTE, this bit is fixed to
“
1
”
(8-bit width).
2:
This bit is valid when the RDY input select bit (bit 2 at address 5F
16
) =
“
1
”
.
3:
When only the external data bus width select bit (bit 2) =
“
1
”
or while V
CC
level voltage is applied to pin BYTE, the
normal access is selected regardless of this bit
’
s contents.
4:
In the single-chip mode, this bit
’
s contents are invalid. (CS
0
output is disabled.)
“
0
”
at read.
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