參數(shù)資料
型號(hào)： M37902FJCHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁(yè)數(shù)： 82/143頁(yè)
文件大?。?/td> 1463K
代理商： M37902FJCHP
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M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
82
Fig. 85 Real-time output structure in pulse mode 0
(2) Pulse mode 1
When the pulse output mode select bit is set to
“
1
”
, the microcom-
puter enters pulse mode 1, and a pulse output port pins are sepa-
rately controlled (6 bits and 2 bits).
Figures 86 shows the real-time output structure in pulse mode 1.
When the waveform output select bits are set to
“
01
”
(bit 1 =
“
0
”
and
bit 0 =
“
1
”
), RTP1
3
to RTP1
0
, RTP0
3
, and RTP0
2
become program-
mable I/O port pins. Simultaneously, RTP0
1
and RTP0
0
become
pulse output port pins.
When the waveform output select bits are set to
“
10
”
(bit 1 =
“
1
”
and
bit 0 =
“
0
”
), RTP1
3
to RTP1
0
, RTP0
3
, and RTP0
2
become pulse out-
put port pins. At this time, RTP0
1
and RTP0
0
become programmable
I/O port pins.
When the waveform output select bits are set to
“
11
”
(bit 1 = bit 0 =
T
D Q
T
D Q
T
D Q
T
D Q
T
D Q
D Q
T
D Q
T
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Timer A0
Timer A2
P5
3
/RTP0
3
P5
2
/RTP0
2
P5
1
/RTP0
1
P5
0
/RTP0
0
Port P5
i
latch
Waveform output select bit (Address A0
16
) bit 1
Pulse output data register 0
(Address A2
16
)
Pulse output data register 1
(Address A4
16
)
D
Pulse output mode select bit
(Address A0
16
)
0
D
7
T
D Q
a
a
a
a
a
a
a
a
Waveform output select bit (Address A0
16
) bit 0
P5
7
/RTP1
3
P5
6
/RTP1
2
P5
5
/RTP1
1
P5
4
/RTP1
0
Port P5
i
direction register
“
1
”
“
0
”
(i = 7 to 0)
a
(Address D
16
)
(Address B
16
)
“
1
”
), pulse output port pins are divided into two groups; one consists
of RTP1
3
to RTP1
0
, RTP0
3
, RTP0
2
and the other consists of RTP0
1
and RTP0
0
.
When the waveform output select bits are set to
“
00
”
(bit 1 = bit 0 =
“
0
”
), port P5 pins become normal programmable I/O port pins.
RTP1
3
to RTP1
0
, RTP0
3
, and RTP0
2
are controlled by timer A2.
Also, RTP0
1
and RTP0
0
are controlled by timer A0.
The contents of the pulse output data register 1 (high-order 6 bits at
address A4
16
), which corresponds to RTP1
3
to RTP1
0
, RTP0
3
, and
RTP0
2
, are output to this port each time when the contents of timer
A2 counter becomes
“
0000
16
”
. The contents of the pulse output data
register 0 (low-order 2 bits at address A2
16
), which corresponds to
RTP0
1
and RTP0
0
, are output to this port each time when the con-
tents of timer A0 counter become
“
0000
16
”
.
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