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12. DMAC
Figure 12.4
DRA0 to DRA3 Registers, DCT0 to DCT3 Registers, DRC0 to DRC3 Registers
b23
Symbol
DRA0
DRA1
DRA2 (SVP)(2)
DRA3 (VCT)(3)
Address
(CPU internal register)
After Reset
XXXXXXh
b0
Function
RW
DMAi Memory Address Reload Register(1) (i = 0 to 3)
RW
Set a incremented source address or incremented destination
address (1)
NOTES:
1. Use the LDC instruction to set registers DRA0 and DRA1.
2. To set the DRA2 register, write to the SVP register using the LDC instruction.
3. To set the DRA3 register, write to the VCT register using the LDC instruction.
Setting Range
000000h to FFFFFFh
(16 Mbytes)
b16 b15
b8 b7
Symbol
DCT0(2)
DCT1(2)
DCT2 (bank1:R0)(3)
DCT3 (bank1:R1)(4)
Address
(CPU internal register)
After Reset
XXXXh
0000h
Function
RW
DMAi Transfer Count Register (i = 0 to 3)
RW
Set the number of transfers
NOTES:
1. When the DCTi register is set to 0000h, no data transfer occurs regardless of a DMA request generation.
2. Use the LDC instruction to set registers DCT0 and DCT1.
3. To set the DCT2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R0 register using the MOV
instruction.
4. To set the DCT3 register, set the B flag to 1 and write to the R1 register using the MOV instruction.
Setting Range
0000h to FFFFh(1)
b15
b0
b8 b7
b15
Symbol
DRC0(1)
DRC1(1)
DRC2 (bank1:R2)(2)
DRC3 (bank1:R3)(3)
Address
(CPU internal register)
After Reset
XXXXh
0000h
b0
Function
RW
DMAi Transfer Count Reload Register (i = 0 to 3)
RW
Set the number of transfers
NOTES:
1. Use the LDC instruction to set registers DRC0 and DRC1.
2. To set the DRC2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R2 register using the MOV
instruction.
3. To set the DRC3 register, set the B flag to 1 and write to the R3 register using the MOV instruction.
Setting Range
0000h to FFFFh
b8 b7