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22. 16-Slot CAN Module
22.1.16 CANi Mode Register (CiMDR Register) (i = 0, 1)
Figure 22.19
C0MDR and C1MDR Registers
22.1.16.1 CMOD Bit
The CMOD bit selects a CAN operating mode.
Normal operating mode: Normal transmit and receive operations are enabled.
Bus monitoring mode(1): Only receive operation is enabled. Output signal from the CANiOUT pin is fixed
to high level (“H”) in bus monitoring mode. The CAN module transmits neither ACK nor error frame.
Self-test mode: The CAN module connects the CANiOUT pin to the CANiIN pin internally. The CAN
module can communicate without additional device when using self-test mode and loop back mode. Output
signal from the CANiOUT pin is fixed to “H” in self-test mode while transmitting.
Figure 22.20 shows an
image diagram in self-test mode.
NOTE:
1. Do not generate a transmit request in bus monitoring mode.
The CAN module in bus monitoring mode considers dominant “L” is received regardless of whether the
actual ACK bit is dominant “L” or recessive “H”. Therefore, when a transmit operation is completed at
EOF, the CAN module determines a receive operation is successfully completed even if the ACK bit is
recessive “H”.
Bit Name
b7 b6 b5 b4
b1
b2
b3
Symbol
C0MDR
C1MDR
Address
0219h
0299h
After Reset(2)
XXXX XX00b
b0
Function
RW
(b7-b2)
CANi Mode Register (i = 0, 1)(1)
RW
NOTES:
1. Set the CiMDR register while the STATE_RESET bit in the CiSTR register is 1 (CAN module is in reset).
2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the
clock to the CAN module.
CAN operating mode
select bit
CMOD
b1 b0
0 0: Normal operating mode
0 1: Bus monitoring mode
1 0: Self-test mode
1 1: Do not set to this value
Bit Symbol
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined