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Figure 16.16
Receive Operation in UART Mode
16.1.2.1 Baud Rate
In UART mode, the baud rate is the clock frequency divided by the setting value of the UiBRG register (i = 0 to
4) and again divided by 16.
Table 16.12 lists an example of baud rate setting.
Table 16.12
Baud Rate
Baud
Rate
UiBRG
Count
Source
Peripheral Clock: 16MHz
Peripheral Clock: 24MHz
Peripheral Clock: 32MHz
UiBRG
Setting Value:
n
Actual Baud
Rate
UiBRG
Setting Value:
n
Actual Baud
Rate
UiBRG
Setting Value:
n
Actual Baud
Rate
1200
f8
103(67h)
1202
155(9Bh)
1202
207(CFh)
1202
2400
f8
51(33h)
2404
77(4Dh)
2404
103(67h)
2404
4800
f8
25(19h)
4808
38(26h)
4808
51(33h)
4808
9600
f1
103(67h)
9615
155(9Bh)
9615
207(CFh)
9615
14400
f1
68(44h)
14493
103(67h)
14423
138(8Ah)
14388
19200
f1
51(33h)
19231
77(4Dh)
19231
103(67h)
19231
28800
f1
34(22h)
28571
51(33h)
28846
68(44h)
28986
31250
f1
31(1Fh)
31250
47(2Fh)
31250
63(3Fh)
31250
38400
f1
25(19h)
38462
38(26h)
38462
51(33h)
38462
51200
f1
19(13h)
50000
28(1Ch)
51724
38(26h)
51282
Count source of
UiBRG register
RE bit in
UiC1 register
i = 0 to 4
NOTE:
1. The above applies when the PRYE bit in the UiMR register is set to 0 (parity disabled), the STPS bit in the UiMR register is set to 0 (1 stop bit),
and the CRS bit in the UiC0 register is set to 1 (CTS function not selected).
Set to 0 by an interrupt request acknowledgement or by program
Internal Clock
8-bit long data receive timing (parity disabled and 1 stop bit)
Input to RXDi
1
0
"H"
"L"
RI bit in
UiC1 register
Stop bit
Start bit
Capture received data
Check if an "L"
signal is applied
Data is transferred from the UARTi
transmit register to the UiRB register
Output from RTSi
D1
D7
D0
The internal clock is generated at
the falling edge of the start bit
and receive operation is started
Change to "L" by reading the UiRB register
IR bit in
SiRIC register
1
0
1
0
Actual baud rate =
UiBRG register count source
16 × (UiBRG register setting value + 1)