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27. Usage Notes
Rev.1.00
27.9.3
Timer B
27.9.3.1
Timer B (Timer Mode, Event Counter Mode)
The TBiS bit (i = 0 to 5) in the TABSR register is set to 0 (count stops) after reset. Set the TBiS bit to 1
(count starts) after selecting operating mode and setting the TBi register.
Bits TB2S to TB0S are bits 7 to 5 in the TABSR register. Bits TB5S to TB3S are bits 7 to 5 in the TBSR
register.
The TBi register indicates a counter value while counting at any given time. However, FFFFh can be read
in the reload timing. A setting value can be read between setting the TBi register while a counter stops and
starting a counter.
27.9.3.2
Timer B (Pulse Period/Pulse Width Measurement Mode)
The IR bit in the TBiIC register becomes 1 (interrupt requested) when the valid edge of measurement pulse
is input and when timer Bi overflows. The MR3 bit in the TBiMR register determines an interrupt request
source within the interrupt routine.
To set the MR3 bit to 0 (no overflow), write to the TBiMR register at the next count timing or later after the
MR3 bit becomes 1, while the TBiS bit in the TABSR register is set to 1 (count starts). (Technical update:
TN-M16C-75-0110)
Use the MR3 bit to determine only an interrupt request source within the interrupt routine.
When the first valid edge is input after the count starts, an undefined value is transferred to the reload
register. At this time, the timer Bi interrupt request is not generated.
The counter value is undefined when the count starts. Therefore, the MR3 bit may become 1 (overflow) and
causes a timer Bi interrupt request to be generated before a valid edge is input.
The IR bit may become 1 (interrupt requested) by changing bits MR1 and MR0 in the TBiMR register after
the count starts. If the same value is written to bits MR1 and MR0, the IR bit setting remains unchanged.
Pulse width is repeatedly measured in pulse width measurement mode. Use a program to determine
whether the measurement result is high (“H”) or low (“L”).