參數(shù)資料
型號(hào)： BX80532KC2800D
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 2800 MHz, MICROPROCESSOR
文件頁數(shù)： 60/129頁
文件大?。?/td> 1640K
代理商： BX80532KC2800D
Intel Xeon Processor with 512 KB L2 Cache
36
Datasheet
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All AC timings for the SMBus signals are referenced at VIL_MAX or VIL_MIN and measured at the processor
pins. Refer to Figure 17.
4. Minimum time allowed between request cycles.
5. Rise time is measured from (VIL_MAX - 0.15V) to (VIH_MIN + 0.15V). Fall time is measured from (0.9 *
SM_VCC) to (VIL_MAX - 0.15V). DC parameters are specified in Table 11.
6. Following a write transaction, an internal device write cycle time of 10ms must be allowed before starting the
next transaction.
2.14
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 14 through Table
Note:
For Figure 6 through Figure 15, the following apply:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal
timings are referenced at GTLREF at the processor core (pads).
2. All source synchronous AC timings for AGTL+ signals are referenced to their associated
strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the
falling edge of their associated data strobe. Source synchronous address signals are referenced
to the rising and falling edge of their associated address strobe. All source synchronous
AGTL+ signal timings are referenced at GTLREF at the processor core (pads).
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All
AGTL+ strobe signal timings are referenced at GTLREF at the processor core (pads).
4. All AC Timing for he TAP signals are referenced to the TCK signal at 0.5 * VCC at the
processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at the 0.5 * VCC at the
processor core (pads).
5. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 * SM_VCC
at the processor pins. All SMBus signal timings (SM_DAT, SM_ALERT#, etc.) are referenced
at VIL_MAX or VIL_MIN at the processor pins.
T79: Bus Free Time
4.7
N/A
S
1, 2, 3, 4,
6
T80: Hold Time after Repeated Start Condition
4.0
N/A
S
1, 2, 3
T81: Repeated Start Condition Setup Time
4.7
N/A
S
1, 2, 3
T82: Stop Condition Setup Time
4.0
N/A
S
1, 2, 3
Table 20. SMBus Signal Group AC Specifications (Page 2 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
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