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| 型號(hào)： | BX80532KC2800D |
| 廠(chǎng)商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR |
| 文件頁(yè)數(shù)： | 120/129頁(yè) |
| 文件大小： | 1640K |
| 代理商： | BX80532KC2800D |
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Intel Xeon Processor with 512 KB L2 Cache
90
Datasheet
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this signal to be a
clean indication that all processor clocks and power supplies are stable and within
their specifications. “Clean” implies that the signal will remain low (capable of
sinking leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition
monotonically to a high state. Figure 13 illustrates the relationship of PWRGOOD to
the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of PWRGOOD. It
must also meet the minimum pulse width specification in Table 16, and be followed
by a 1 mS RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
3
REQ[4:0]#
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
front side bus agents. They are asserted by the current bus owner to define the
currently active transaction type. These signals are source synchronous to
ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking
of these signals.
4
RESET#
I
Asserting the RESET# signal resets all processors to known states and invalidates
their internal caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCC and BCLK
have reached their proper specifications. On observing active RESET#, all front
side bus agents will deassert their outputs within two clocks. RESET# must not be
kept asserted for more than 10ms.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
This signal does not have on-die termination and must be terminated at the
end agent. See the appropriate Platform Design Guideline for additional
information.
4
RS[2:0]#
I
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor front side bus agents.
4
RSP#
I
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to the appropriate pins of all
processor front side bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
4
SKTOCC#
O
SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate
that the processor is present.
SLP#
I
SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the
Sleep state. During Sleep state, the processor stops providing internal clock signals
to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in
this state will not recognize snoops or interrupts. The processor will recognize only
assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK
input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop-Grant state, restarting its internal clock signals to the bus and
processor core units.
3
SM_ALERT#
O
SM_ALERT# is an asynchronous interrupt line associated with the SMBus Thermal
Sensor device. It is an open-drain output and the processor includes a 10 K
pull-
up resistor to SM_VCC for this signal. For more information on the usage of the
SM_ALERT# pin, see Section 7.4.5.
Table 41. Signal Definitions (Page 7 of 10)
Name
Type
Description
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BX80524R300128 | 32-BIT, 300 MHz, MICROPROCESSOR, XMA |
| BZV09/A0332/04 | 3A, 250VAC, FEMALE AND MALE, MAINS POWER CONNECTOR |
| BZV09/A0332/14 | 3A, 250VAC, FEMALE AND MALE, MAINS POWER CONNECTOR |
| BZV09/A0332/37 | 3A, 250VAC, FEMALE AND MALE, MAINS POWER CONNECTOR |
| BKT-146-01-F-V | 92 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80532KC2800DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80532KC2800F | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80532KC3000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
| BX80532KC3000H | 制造商:Intel 功能描述:MPU XEON NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
| BX80532KE2000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
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