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參數(shù)資料
| 型號： | BX80532KC2800D |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR |
| 文件頁數(shù)： | 39/129頁 |
| 文件大小： | 1640K |
| 代理商： | BX80532KC2800D |
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Intel Xeon Processor with 512 KB L2 Cache
Datasheet
17
Table 1.
Front Side Bus-to-Core Frequency Ratio
2.4.1
Bus Clock
The front side bus frequency is set to the maximum supported by the individual processor.
BSEL[1:0] are outputs used to select the front side bus frequency. Table 2 defines the possible
combinations of the signals and the frequency associated with each combination. The frequency is
determined by the processor(s), chipset, and clock synthesizer. All front side bus agents must
operate at the same frequency. Individual processors will only operate at their specified front side
bus clock frequency, (100 MHz for present generation processors).
Baseboards designed for the Intel XeonTM processor employ a 100 MHz front side bus clock. On
these baseboards, BSEL[1:0] are considered ‘reserved’ at the processor socket. No change is
required for operation with the Intel Xeon processor with 512 KB L2 cache. Operation will
default to 100 MHz.
Table 2. Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]
2.5
PLL Filter
VCCA and VCCIOPLL are power sources required by the processor PLL clock generator. This
requirement is identical to that of the Intel Xeon processor. Since these PLLs are analog in nature,
they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades
external I/O timings as well as internal core timings (i.e. maximum frequency). To prevent this
degradation, these supplies must be low pass filtered from V
CC. A typical filter topology is shown
in Figure 1.
Front Side Bus-to-Core
Frequency Ratio
Core Frequency
1/16
1.60 GHz
1/17
1.70 GHz
1/18
1.80 GHz
1/19
1.90 GHz
1/20
2 GHz
1/21
2.10 GHz
1/22
2.20 GHz
1/24
2.40 GHz
1/26
2.60 GHz
1/28
2.80 GHz
1/30
3 GHz
BSEL1
BSEL0
Bus Clock Frequency
L
100 MHz
LH
Reserved
HL
Reserved
HH
Reserved
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