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參數(shù)資料
| 型號： | BX80532KC2800D |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR |
| 文件頁數(shù)： | 122/129頁 |
| 文件大?。?/td> | 1640K |
| 代理商： | BX80532KC2800D |
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Intel Xeon Processor with 512 KB L2 Cache
92
Datasheet
TESTHI[6:0]
I
All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor
which matches the trace impedance within a range of ±10 ohms. TESTHI[3:0] and
TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if
desired. However, utilization of boundary scan test will not be functional if these
pins are connected together. TESTHI4 must always be pulled up independently
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values
used for TESTHI[6:0] pins should have a resistance value within ±20 percent of the
impedance of the baseboard transmission line traces. For example, if the trace
impedance is 50
, then a value between 40 and 60 should be used. The
TESTHI[6:0] termination recommendations provided in the Intel XeonTM
processor datasheet are still suitable for the Intel XeonTM processor with 512 KB
L2 cache. However, Intel recommends new designs or designs undergoing design
updates follow the trace impedance matching termination guidelines given in this
section.
THERMTRIP#
O
Activation of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor which is configured to trip at approximately 135 °C. To properly
protect the processor, power must be removed upon THERMTRIP# becoming
active. See Figure 16 and Table 20 for the appropriate power down sequence and
timing requirement. In parallel, the processor will attempt to reduce its temperature
by shutting off internal clocks and stopping all program execution. Once activated,
THERMTRIP# remains latched and the processor will be stopped until RESET# is
asserted. A RESET# pulse will reset the processor and execution will begin at the
boot vector. If the temperature has not dropped below the trip level, the processor
will assert THERMTRIP# and return to the shutdown state. The processor releases
THERMTRIP# when RESET# is activated even if the processor is still too hot.
This signal do not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guidelines for additional
information
.
2
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
This signal does not have on-die termination and must be terminated at the
end agent.See the appropriate platform design guidelines for additional
information
.
TRDY#
I
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all front side bus agents.
TRST#
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset. See the appropriate Platform Design Guideline for
additional information
.
VCCA
I
VCCA provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to
provide clean power to the PLL. The tolerance and total ESR for the filter is
important. Refer to the appropriate platform design guidelines for complete
implementation details.
VCCIOPLL
I
VCCIOPLL provides isolated power for digital portion of the internal PLL’s. Follow the
guidelines for VCCA (Section 2.5), and refer to the appropriate platform design
guidelines for complete implementation details.
VCCSENSE
VSSSENSE
O
The Vccsense and Vsssense pins are the points for which processor minimum and
maximum voltage requirements are specified. Uniprocessor designs may utilize
these pins for voltage sensing for the processor's voltage regulator. However, multi-
processor designs must not connect these pins to sense logic, but rather utilize
them for power delivery validation
.
Table 41. Signal Definitions (Page 9 of 10)
Name
Type
Description
Notes
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PDF描述 |
|---|---|
| BX80524R300128 | 32-BIT, 300 MHz, MICROPROCESSOR, XMA |
| BZV09/A0332/04 | 3A, 250VAC, FEMALE AND MALE, MAINS POWER CONNECTOR |
| BZV09/A0332/14 | 3A, 250VAC, FEMALE AND MALE, MAINS POWER CONNECTOR |
| BZV09/A0332/37 | 3A, 250VAC, FEMALE AND MALE, MAINS POWER CONNECTOR |
| BKT-146-01-F-V | 92 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80532KC2800DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80532KC2800F | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80532KC3000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
| BX80532KC3000H | 制造商:Intel 功能描述:MPU XEON NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
| BX80532KE2000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
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