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| 型號(hào)： | BX80532KC2800D |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR |
| 文件頁(yè)數(shù)： | 115/129頁(yè) |
| 文件大?。?/td> | 1640K |
| 代理商： | BX80532KC2800D |
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Intel Xeon Processor with 512 KB L2 Cache
86
Datasheet
BR0#
BR[1:3]#1
I/O
I
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual processor
pins. BR2# and BR3# must not be utilized in a dual processor platform design. The
table below gives the rotating interconnect between the processor and bus signals
for dual processor systems.
During power-on configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition
of RESET#. The pin which the agent samples asserted determines it’s agent ID.
These signals do not have on-die termination and must be terminated at the
end agent. See the appropriate platform design guidelines for additional
information.
1,4
BSEL[1:0]
O
These output signals are used to select the front side bus frequency. A BSEL[1:0] =
“00” will select a 100 MHz bus clock frequency. The frequency is determined by the
processor(s), chipset, and frequency synthesizer capabilities. All front side bus
agents must operate at the same frequency. Individual processors will only operate
at their specified front side bus (FSB) frequency.
On baseboards which support operation only at 100 MHz bus clocks these signals
can be ignored. On baseboards employing the use of these signals, a 1 K
pull-up
resistor be used.
page 17 for output values.
COMP[1:0]
I
COMP[1:0] must be terminated to VSS on the baseboard using precision resistors.
These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate
platform design guidelines and Table 13 for implementation details.
Table 41. Signal Definitions (Page 3 of 10)
Name
Type
Description
Notes
BR[1:0]# Signals Rotating Interconnect, dual processor system
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its agent
ID. All agents then configure their pins to match the appropriate bus signal protoco
as shown below.
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
BR[1:0]# Signal Agent IDs
BR[1:0]# Signals Rotating
Interconnect, dual processor system
Agent ID
BR0#
0
BR1#
1
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相關(guān)代理商/技術(shù)參數(shù) |
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| BX80532KC2800DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80532KC2800F | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
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| BX80532KC3000H | 制造商:Intel 功能描述:MPU XEON NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
| BX80532KE2000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2GHZ - Boxed Product (Development Kits) |
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