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參數(shù)資料
| 型號： | BX80532KC2800D |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR |
| 文件頁數(shù)： | 54/129頁 |
| 文件大?。?/td> | 1640K |
| 代理商： | BX80532KC2800D |
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Intel Xeon Processor with 512 KB L2 Cache
30
Datasheet
3. TAP signal group must meet the system signal quality specification in Chapter 3.0.
4. Refer to the Intel Xeon Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
5. The VCC referred to in these specifications refers to instantaneous VCC.
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
7. VOL_MAX of 0.300V is guaranteed when driving a test load.
8. VHYS represents the amount of hysteresis, nominally centered about 0.5*VCC, for all TAP inputs.
9. Leakage to VCC with Pin held at 300 mV.
10.Leakage to VSS with pin held at VCC.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All outputs are open drain
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
5. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.0.
6. Refer to the Intel Xeon Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
7. The VCC referred to in these specifications refers to instantaneous VCC.
8. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
9. VOL_MAX of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with RTT enabled.
10. Leakage to VCC with Pin held at 300 mV.
11. Leakage to VSS with pin held at VCC.
Table 11. SMBus Signal Group DC Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All DC specifications for the SMBus signal group are measured at the processor pins.
4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
maximum rise and fall times for SMBus signals.
Table 10. Asynchronous GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1, 7
VIH
Input High Voltage
1.10 * GTLREF
VCC
V3, 5, 7
VIL
Input Low Voltage
0.0
0.90 * GTLREF
V
4, 6
VOH
Output High Voltage
N/A
VCC
V2, 5, 7
IOL
Output Low Current
50
mA
8, 9
IHI
Pin Leakage High
N/A
100
A
11
ILO
Pin Leakage Low
N/A
500
A
10
RON
Buffer On Resistance
7
11
6
Symbol
Parameter
Min
Max
Unit
Notes 1, 2, 3
VIL
Input Low Voltage
-0.30
0.30 * SM_VCC
V
VIH
Input High Voltage
0.70 * SM_VCC
3.465
V
VOL
Output Low Voltage
0
0.400
V
IOL
Output Low Current
N/A
3.0
mA
ILI
Input Leakage Current
N/A
± 10
A
ILO
Output Leakage Current
N/A
± 10
A
CSMB
SMBus Pin Capacitance
15.0
pF
4
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