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參數(shù)資料
| 型號： | BX80532KC2800D |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR |
| 文件頁數(shù)： | 56/129頁 |
| 文件大?。?/td> | 1640K |
| 代理商： | BX80532KC2800D |
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Intel Xeon Processor with 512 KB L2 Cache
32
Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The tolerances for this specification have been stated generically to enable system designer to calculate the
minimum values across the range of VCC.
3. GTLREF is generated from VCC on the baseboard by a voltage divider of 1 percent resistors. Refer to the
appropriate platform design guidelines for implementation details.
4. RTT is the on-die termination resistance measured from VCC to 1/3 VCC at the AGTL+ output driver. Refer to
the Intel Xeon Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
5. COMP resistors are pull downs to VSS provided on the baseboard with 1% tolerance. See the appropriate
platform design guidelines for implementation details.
6. The VCC referred to in these specifications refers to instantaneous VCC.
7. The COMP resistance value varies by platform. Refer to the appropriate platform design guideline for the
recommended COMP resistance value.
8. The values for RTT and COMP noted as ‘New Designs’ apply to designs that are optimized for the Intel
Xeon processor with 512 KB L2 cache. Refer to the appropriate platform design guideline for the
recommended COMP resistance value.
9. This specification applies to the Intel XeonProcessor with 512 KB L2 Cache
when implemented in
platforms that do not include forward compatibility with future processors.
10.This specification applies to the Intel Xeon Processor with 512 KB L2 Cache when implemented in platforms
that include forward compatibility with future processors.
2.13
Front Side Bus AC Specifications
The processor front side bus timings specified in this section are defined at the processor core
(pads). See Section 5.0 for the pin listing and signal definitions.
All AGTL+ timings are referenced to GTLREF for both ‘0’ and ‘1’ logic levels unless otherwise
specified.
The timings specified in this section should be used in conjunction with the signal integrity models
provided by Intel. These signal integrity models, which include package information, are available
for the Intel Xeon processor with 512 KB L2 cache in IBIS format. AGTL+ layout guidelines
are also available in the appropriate platform design guidelines.
Note: Care should be taken to read all notes associated with a particular timing parameter
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
COMP[1:0]
New
Design
COMP Resistance
49.55
50
50.45
5, 7, 8
Table 13. AGTL+ Bus Voltage Definitions
Table 14. Front Side Bus Differential Clock Specifications
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
Front Side Bus Clock Frequency
100.0
MHz
1, 2
T1: BCLK[1:0] Period
10.00
10.20
nS
1, 3
T2: BCLK[1:0] Period Stability
N/A
150
pS
1, 4, 5
T3: TPH BCLK[1:0] Pulse High Time
3.94
5
6.12
nS
1
T4: TPL BCLK[1:0] Pulse Low Time
3.94
5
6.12
nS
1
T5: BCLK[1:0] Rise Time
175
700
pS
1, 6
T6: BCLK[1:0] Fall Time
175
700
pS
1, 6
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