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| 型號： | UPD703130GC-8EU |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 46/72頁 |
| 文件大?。?/td> | 601K |
| 代理商： | UPD703130GC-8EU |
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Preliminary Data Sheet U15390EJ1V0DS
46
μ
PD703130
(e) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to CLKOUT
↑
)
<26>
t
SKID
18
ns
Data input hold time (from CLKOUT
↑
)
<27>
t
HKID
2
ns
Delay time from OE
↑
to data output
<37>
t
DRDOD
(0.5 + i)T – 10
ns
Row address setup time
<56>
t
ASR
(0.5 + w
RP
)T – 10
ns
Row address hold time
<57>
t
RAH
(0.5 + w
RH
)T – 10
ns
Column address setup time
<58>
t
ASC
0.5T – 10
ns
Column address hold time
<59>
t
CAH
(0.5 + w
DA
)T – 10
ns
RAS precharge time
<61>
t
RP
(0.5 + w
RP
)T – 10
ns
Column address read time (from RAS
↑
)
<64>
t
RAL
(2 + w
CP
+ w
DA
)T – 10
ns
CAS-RAS precharge time
<66>
t
CRP
(1 + w
RP
)T – 10
ns
CAS hold time
<67>
t
CSH
(1.5 + w
RH
+ w
DA
)
T –
10
ns
WE setup time (to CAS
↓
)
<68>
t
RCS
(2 + w
RP
+ w
RH
)T – 10
ns
WE hold time (from RAS
↑
)
<69>
t
RRH
0.5T – 10
ns
WE hold time (from CAS
↑
)
<70>
t
RCH
1.5T – 10
ns
RAS access time
<73>
t
RAC
(2 + w
RH
+ w
DA
)
T –
28
ns
Access time from column address
<74>
t
AA
(1.5 + w
DA
)T – 28
ns
CAS access time
<75>
t
CAC
(1 + w
DA
)T – 28
ns
Delay time from RAS to column address
<76>
t
RAD
(0.5 + w
RH
)T – 10
ns
RAS-CAS delay time
<77>
t
RCD
(1 + w
RH
)T – 10
ns
Output buffer turn-off delay time (from
OE)
<78>
t
OEZ
0
ns
Access time from CAS precharge
<80>
t
ACP
(1.5 + w
CP
+ w
DA
)
T –
28
ns
CAS precharge time
<81>
t
CP
(0.5 + w
CP
)T – 10
ns
RAS hold time for CAS precharge
<83>
t
RHCP
(2 + w
CP
+ w
DA
)T – 10
ns
Read cycle time
<93>
t
HPC
(1 + w
DA
+ w
CP
)T – 10
ns
RAS pulse width
<94>
t
RASP
(2.5 + w
RH
+ w
DA
)
T –
10
ns
CAS pulse width
<95>
t
HCAS
(0.5 + w
DA
)T – 10
ns
Off-page
<96>
t
OCH1
(2 + w
RH
+ w
DA
)T – 10
ns
CAS hold time from OE
On-page
<97>
t
OCH2
(0.5 + w
DA
)T – 10
ns
Data input hold time (from CAS
↓
)
<98>
t
DHC
0
ns
Remarks 1.
T = t
CYK
2.
w
RP
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
w
RH
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
w
DA
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5.
w
CP
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
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