參數(shù)資料
型號: UPD703130GC-8EU
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 34/72頁
文件大?。?/td> 601K
代理商: UPD703130GC-8EU
Preliminary Data Sheet U15390EJ1V0DS
34
μ
PD703130
(5) Page ROM access timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT
)
<24>
t
SWK
15
ns
WAIT hold time (from CLKOUT
)
<25>
t
HKW
2
ns
Data input setup time
(to CLKOUT
)
<26>
t
SKID
18
ns
Data input hold time
(from CLKOUT
)
<27>
t
HKID
2
ns
Off-page data input setup time (to
address)
<30>
t
SAID
(1.5 + w
D
+ w)T – 28
ns
Off-page data input setup time (to RD)
<31>
t
SRDID
(1 + w
D
+ w)T – 32
ns
Off-page RD low-level width
<32>
t
WRDL
(1 + w
D
+ w)T – 10
ns
RD high-level width
<33>
t
WRDH
0.5T – 10
ns
Data input hold time (from RD)
<36>
t
HRDID
0
ns
Delay time from RD
to data output
<37>
t
DRDOD
(0.5 + i)T – 10
ns
On-page RD low-level width
<53>
t
WORDL
(1.5 + w
PR
+ w)T
– 10
ns
On-page data input setup time
(to address)
<54>
t
SOAID
(1.5 + w
PR
+ w)T – 28
ns
On-page data input setup time (to RD)
<55>
t
SORDID
(1.5 + w
PR
+ w)T – 32
ns
Remarks 1.
T = t
CYK
2.
w: The number of waits due to WAIT.
3.
w
D
: The number of waits due to the DWC1 and DWC2 registers.
4.
w
PR
: The number of waits due to the PRC register.
5.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
6.
Maintain at least one of the data input hold times, t
HKID
or t
HRDID
.
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