參數(shù)資料
型號(hào): UPD703130GC-8EU
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁(yè)數(shù): 41/72頁(yè)
文件大小: 601K
代理商: UPD703130GC-8EU
Preliminary Data Sheet U15390EJ1V0DS
41
μ
PD703130
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2.
The broken lines indicate high impedance.
3.
n = 3 to 5
TCPW
TO1
TDAW
TO2
<58>
<59>
<63>
<64>
<83>
<65>
<81>
<82>
<68>
<75>
<72>
<26>
<79>
<37>
<74>
<80>
<27>
<78>
<70>
<69>
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
WE (Output)
OE (Output)
D0 to D15 (I/O)
WAIT (Input)
Column address
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