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TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
6-1
TMS320F28335 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
............................
108
TMS320F28334 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
............................
109
TMS320F28332 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
...........................
110
Typical Current Consumption by Various Peripherals (at 150 MHz)
.....................................................
111
Clocking and Nomenclature (150-MHz devices)
............................................................................
115
Clocking and Nomenclature (100-MHz devices)
............................................................................
115
Input Clock Frequency
..........................................................................................................
116
XCLKIN Timing Requirements - PLL Enabled
...............................................................................
116
XCLKIN Timing Requirements - PLL Disabled
..............................................................................
116
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
.......................................................
116
Power Management and Supervisory Circuit Solutions
....................................................................
117
Reset (XRS) Timing Requirements
...........................................................................................
119
General-Purpose Output Switching Characteristics
.........................................................................
120
General-Purpose Input Timing Requirements
...............................................................................
121
IDLE Mode Timing Requirements
.............................................................................................
123
IDLE Mode Switching Characteristics
.........................................................................................
123
STANDBY Mode Timing Requirements
......................................................................................
123
STANDBY Mode Switching Characteristics
.................................................................................
124
HALT Mode Timing Requirements
............................................................................................
124
HALT Mode Switching Characteristics
.......................................................................................
125
ePWM Timing Requirements
...................................................................................................
126
ePWM Switching Characteristics
..............................................................................................
126
Trip-Zone input Timing Requirements
........................................................................................
126
High Resolution PWM Characteristics at SYSCLKOUT = (60 - 150 MHz)
..............................................
127
Enhanced Capture (eCAP) Timing Requirement
............................................................................
127
eCAP Switching Characteristics
...............................................................................................
127
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
....................................................
127
eQEP Switching Characteristics
...............................................................................................
127
External ADC Start-of-Conversion Switching Characteristics
..............................................................
127
External Interrupt Timing Requirements
......................................................................................
128
External Interrupt Switching Characteristics
.................................................................................
128
I2C Timing
.......................................................................................................................
129
SPI Master Mode External Timing (Clock Phase = 0)
......................................................................
130
SPI Master Mode External Timing (Clock Phase = 1)
......................................................................
132
SPI Slave Mode External Timing (Clock Phase = 0)
........................................................................
133
SPI Slave Mode External Timing (Clock Phase = 1)
........................................................................
134
Relationship Between Parameters Configured in XTIMING and Duration of Pulse
....................................
135
XINTF Clock Configurations
....................................................................................................
137
External Interface Read Timing Requirements
..............................................................................
139
External Interface Read Switching Characteristics
..........................................................................
139
External Interface Write Switching Characteristics
..........................................................................
140
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
List of Tables
8
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