參數(shù)資料
型號(hào): TMS320F28335_1
廠商: Texas Instruments, Inc.
英文描述: Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述: 數(shù)字信號(hào)控制器(DSC)
文件頁(yè)數(shù): 40/166頁(yè)
文件大?。?/td> 1889K
代理商: TMS320F28335_1
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A
3.2.2
Memory Bus (Harvard Bus Architecture)
3.2.3
Peripheral Bus
3.2.4
Real-Time J TAG and Analysis
3.2.5
External Interface (XINTF)
3.2.6
Flash
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal
latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This
pipelining enables it to execute at high speeds without resorting to expensive high-speed memories.
Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store
conditional operations further improve performance.
As with many DSC type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
To enable migration of peripherals between various Texas Instruments (TI) DSC family of devices, the
F2833x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus
are supported on the F2833x. One version supports only 16-bit accesses (called peripheral frame 2).
Another version supports both 16- and 32-bit accesses (called peripheral frame 1). The third version
supports DMA access and both 16- and 32-bit accesses (called peripheral frame 3).
The F2833x implements the standard IEEE 1149.1 JTAG interface. Additionally, the F2833x supports
real-time mode of operation whereby the contents of memory, peripheral and register locations can be
modified while the processor is running and executing code and servicing interrupts. The user can also
single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The F2833x implements the real-time mode in hardware within the CPU. This is a unique
feature to the F2833x, no software monitor is required. Additionally, special analysis hardware is provided
which allows the user to set hardware breakpoint or data/address watch-points and generate various
user-selectable break events when a match occurs.
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The
chip-select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be
programmed with a different number of wait states, strobe signal setup and hold timing and each zone can
be programmed for extending wait states externally or not. The programmable wait-state, chip-select and
programmable strobe timing enables glueless interface to external memories and peripherals.
The F28335 contains 256K
×
16 of embedded flash memory, segregated into eight 32K
×
16 sectors. The
F28334 contains 128K
×
16 of embedded flash memory, segregated into eight 16K
×
16 sectors. The
F28332 device contains 64K
×
16 of embedded flash, segregated into four 16K
×
16 sectors. All the
Functional Overview
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TMS320F28335PGFA 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Signal Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320F28335PGFA 制造商:Texas Instruments 功能描述:IC DSC 32BIT 512KB 150MHZ 1.995V LQFP176
TMS320F28335PTPQ 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Delfino Micrcntrlr RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320F28335PTPS 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Delfino Micrcntrlr RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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