參數(shù)資料
型號: TMS320F28335_1
廠商: Texas Instruments, Inc.
英文描述: Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述: 數(shù)字信號控制器(DSC)
文件頁數(shù): 24/166頁
文件大?。?/td> 1889K
代理商: TMS320F28335_1
www.ti.com
A
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
Table 2-2. Signal Descriptions (continued)
PIN NO.
ZHH
BAL
L #
PGF
PIN
#
ZJ Z
BAL
L #
NAME
DESCRIPTION
(1)
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.9-V core digital
power supply. A 1.9-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1
must be tied to GND. (I)
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)
X1
104
J13
G14
X2
102
J11
H14
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSC when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD,
)
The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.
XRS
80
L10
M13
ADC SIGNALS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCLO
ADCRESEXT
ADCREFIN
35
36
37
38
39
40
41
42
53
52
51
50
49
48
47
46
43
57
54
K4
J5
L1
L2
L3
M1
N1
M3
K5
P4
N4
M4
L4
P3
N3
P2
M2
M5
L5
K1
K2
L1
L2
L3
M1
M2
M3
N6
M6
N5
M5
N4
M4
N3
P3
N2
P6
P7
ADC Group A, Channel 7 input (I)
ADC Group A, Channel 6 input (I)
ADC Group A, Channel 5 input (I)
ADC Group A, Channel 4 input (I)
ADC Group A, Channel 3 input (I)
ADC Group A, Channel 2 input (I)
ADC Group A, Channel 1 input (I)
ADC Group A, Channel 0 input (I)
ADC Group B, Channel 7 input (I)
ADC Group B, Channel 6 input (I)
ADC Group B, Channel 5 input (I)
ADC Group B, Channel 4 input (I)
ADC Group B, Channel 3 input (I)
ADC Group B, Channel 2 input (I)
ADC Group B, Channel 1 input (I)
ADC Group B, Channel 0 input (I)
Low Reference (connect to analog ground) (I)
ADC External Current Bias Resistor. Connect a 22-k
resistor to analog ground.
External reference input (I)
Internal Reference Positive Output. Requires a low ESR (50 m
- 1.5
) ceramic bypass capacitor
of 2.2
μ
F to analog ground. (O)
Internal Reference Medium Output. Requires a low ESR (50 m
- 1.5
) ceramic bypass capacitor
of 2.2
μ
F to analog ground. (O)
ADCREFP
56
P5
P5
ADCREFM
55
N5
P4
CPU AND I/O POWER PINS
V
DDA2
V
SSA2
V
DDAIO
V
SSAIO
V
DD1A18
V
SS1AGND
V
DD2A18
V
SS2AGND
34
33
45
44
31
32
59
58
K2
K3
N2
P1
J4
K1
M6
K6
K4
P1
L5
N1
K3
L4
L6
P2
ADC Analog Power Pin
ADC Analog Ground Pin
ADC Analog I/O Power Pin
ADC Analog I/O Ground Pin
ADC Analog Power Pin
ADC Analog Ground Pin
ADC Analog Power Pin
ADC Analog Ground Pin
Introduction
24
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