參數(shù)資料
型號: TMS320F28335_1
廠商: Texas Instruments, Inc.
英文描述: Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述: 數(shù)字信號控制器(DSC)
文件頁數(shù): 74/166頁
文件大?。?/td> 1889K
代理商: TMS320F28335_1
www.ti.com
A
4.7.1
ADC Connections if the ADC Is Not Used
4.7.2
ADC Registers
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
NOTE
The temperature rating of any recommended component must match the rating of the end
product.
It is recommended to keep the connections for the analog power pins, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:
V
DD1A18
/V
DD2A18
– Connect to V
DD
V
DDA2
, V
DDAIO
– Connect to V
DDIO
V
SS1AGND
/V
SS2AGND
, V
SSA2
, V
SSAIO
– Connect to V
SS
ADCLO – Connect to V
SS
ADCREFIN – Connect to V
SS
ADCREFP/ADCREFM – Connect a 100-nF cap to V
SS
ADCRESEXT – Connect a 20-k
resistor (very loose tolerance) to V
SS
.
ADCINAn, ADCINBn - Connect to V
SS
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (V
SS1AGND
/V
SS2AGND
)
NOTE
ADC parameters for gain error and offset error are specified only if the ADC calibration
routine is executed from the Boot ROM. See
Section 4.7.3
for more information.
The ADC operation is configured, controlled, and monitored by the registers listed in
Table 4-5
.
Table 4-5. ADC Registers
(1)
NAME
ADCTRL1
ADCTRL2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADDRESS
(1)
0x7100
0x7101
0x7102
0x7103
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x710D
ADDRESS
(2)
SIZE (x16)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
ADC Control Register 1
ADC Control Register 2
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
0x0B00
0x0B01
0x0B02
0x0B03
0x0B04
0x0B05
(1)
(2)
The registers in this column are Peripheral Frame 2 Registers.
The ADC result registers are dual mapped in the F2833x DSC. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and
left justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 1 wait-state for CPU accesses and 0 wait state for DMA
accesses and right justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of
ADC results to user memory.
Peripherals
74
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