參數(shù)資料
型號： TMS320F28335_1
廠商： Texas Instruments, Inc.
英文描述： Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述： 數(shù)字信號控制器（DSC）
文件頁數(shù)： 145/166頁
文件大?。?/td> 1889K
代理商： TMS320F28335_1
www.ti.com
A
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
6.10.7.8
External Interface Ready-on-Write Timing With One External Wait State
Table 6-46. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 low
(1)
Delay time, XCLKOUT high/low to XWE0, XWE1 high
(1)
Delay time, XCLKOUT high to XR/W low
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE0, XWE1 low
(1)
Delay time, data valid after XWE0, XWE1 active low
(1)
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high
(1)
Maximum time for DSP to release the data bus after XR/W inactive high
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
d(XWEL-XD)
t
h(XA)XZCSH
t
h(XD)XWE
t
dis(XD)XRNW
1
3
2
2
2
1
1
– 2
– 2
0
4
(2)
TW-2
(3)
4
(1)
(2)
(3)
XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
TW = trail period, write access (see
Table 6-37
)
Table 6-47. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
(1)
MIN
15
12
MAX
UNIT
ns
ns
ns
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
e(XRDYsynchH)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
3
t
su(XRDYsynchH)XCOHL
t
h(XRDYsynchH)XZCSH
15
0
ns
ns
(1)
The first XREADY (synchronous) sample occurs with respect to E in
Figure 6-27
:
E =(XWRLEAD + XWRACTIVE) t
When first sampled, if XREADY (synchronous) is high, then the access will complete. If XREADY (synchronous) is low, it is sampled
again each t
until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE +n –1) t
– t
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-48. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
(1)
MIN
11
MAX
UNIT
ns
ns
ns
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
8
3
t
su(XRDYasynchH)XCOHL
t
h(XRDYasynchH)XZCSH
11
0
ns
ns
(1)
The first XREADY (synchronous) sample occurs with respect to E in
Figure 6-27
:
E = (XWRLEAD + XWRACTIVE –2) t
. When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each t
until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) t
– t
where n is the sample number: n = 1, 2, 3, and so forth.
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Electrical Specifications
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