參數(shù)資料
型號： TMS320F28335_1
廠商： Texas Instruments, Inc.
英文描述： Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述： 數(shù)字信號控制器（DSC）
文件頁數(shù)： 55/166頁
文件大?。?/td> 1889K
代理商： TMS320F28335_1
www.ti.com
A
3.6.1
OSC and PLL Block
X1
XCLKIN
(3.3-V clock input
from external
oscillator)
On-chip
oscillator
X2
PLLSTS[OSCOFF]
OSCCLK
PLL
VCOCLK
4-bit PLL Select (PLLCR)
OSCCLK or
VCOCLK
CLKIN
OSCCLK
0
PLLSTS[PLLOFF]
n
n
≠
0
PLLSTS[DIVSEL]
/1
/2
/4
External
Crystal or
Resonator
To
CPU
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in
Table 3-15
.
Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers
Name
PLLSTS
Reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PCLKCR3
PLLCR
SCSR
WDCNTR
Reserved
WDKEY
Reserved
WDCR
Reserved
Address
0x0000-7011
Size (x16)
1
7
1
1
1
1
1
1
1
1
1
1
1
1
3
1
6
Description
PLL Status Register
0x0000-7012 - 0x0000-7018
0x0000-701A
0x0000-701B
0x0000-701C
0x0000-701D
0x0000-701E
0x0000-701F
0x0000-7020
0x0000-7021
0x0000-7022
0x0000-7023
0x0000-7024
0x0000-7025
0x0000-7026 - 0x0000-7028
0x0000-7029
0x0000-702A - 0x0000-702F
High-Speed Peripheral Clock Pre-Scaler Register
Low-Speed Peripheral Clock Pre-Scaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
Low Power Mode Control Register 1
Peripheral Clock Control Register 3
PLL Control Register
System Control and Status Register
Watchdog Counter Register
Watchdog Reset Key Register
Watchdog Control Register
Figure 3-9
shows the OSC and PLL block on the F2833x.
Figure 3-9. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the F2833x devices using the
X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the
following configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed V
DDIO
.
2. A 1.9-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed V
DD
.
The three possible input-clock configurations are shown in
Figure 3-10
through
Figure 3-12
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Functional Overview
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