參數(shù)資料
型號: TMS320F28335_1
廠商: Texas Instruments, Inc.
英文描述: Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述: 數(shù)字信號控制器(DSC)
文件頁數(shù): 46/166頁
文件大?。?/td> 1889K
代理商: TMS320F28335_1
www.ti.com
A
3.2.21 Serial Port Peripherals
3.3
Register Map
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
The F2833x devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality
codecs for modem applications or high-quality stereo audio DAC devices. The McBSP
receive and transmit registers are supported by the DMA to significantly reduce the
overhead for servicing this peripheral. Each McBSP module can be configured as an SPI
as required.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSC and external peripherals or another processor. Typical applications include external
I/O or peripheral expansion through devices such as shift registers, display drivers, and
ADCs. Multi-device communications are supported by the master/slave operation of the
SPI. On the F2833x, the SPI contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F2833x, the SCI contains a 16-level receive and transmit FIFO
for reducing interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between a DSC and other
devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version
2.1 and connected by way of an I2C-bus. External components attached to this 2-wire
serial bus can transmit/receive up to 8-bit data to/from the DSC through the I2C module.
On the F2833x, the I2C contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
McBSP:
SPI:
SCI:
I2C:
The F2833x devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:
Peripheral
Frame 1
Peripheral
Frame 2:
Peripheral
Frame 3:
These are peripherals that are mapped directly to the CPU memory bus.
See
Table 3-7
These are peripherals that are mapped to the 32-bit peripheral bus.
See
Table 3-8
These are peripherals that are mapped to the 16-bit peripheral bus.
See
Table 3-9
These are peripherals that are mapped to the 32-bit DMA-accessible peripheral
bus.
See
Table 3-10
Table 3-7. Peripheral Frame 0 Registers
(1)
NAME
Device Emulation Registers
FLASH Registers
(3)
Code Security Module Registers
ADDRESS RANGE
0x00 0880 - 0x00 09FF
0x00 0A80 - 0x00 0ADF
0x00 0AE0 - 0x00 0AEF
SIZE (
×
16)
384
96
16
ACCESS TYPE
(2)
EALLOW protected
EALLOW protected
EALLOW protected
(1)
(2)
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
(3)
Functional Overview
46
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