參數(shù)資料
型號(hào)： TMS320F28335_1
廠商： Texas Instruments, Inc.
英文描述： Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述： 數(shù)字信號(hào)控制器（DSC）
文件頁數(shù)： 57/166頁
文件大?。?/td> 1889K
代理商： TMS320F28335_1
www.ti.com
A
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
Table 3-16. PLLCR
(1)
Bit Descriptions
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE
(2)
0000 (PLL bypass)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011 - 1111
PLLSTS[DIVSEL] = 0 or 1
OSCCLK/4 (Default)
(OSCCLK * 1)/4
(OSCCLK * 2)/4
(OSCCLK * 3)/4
(OSCCLK * 4)/4
(OSCCLK * 5)/4
(OSCCLK * 6)/4
(OSCCLK * 7)/4
(OSCCLK * 8)/4
(OSCCLK * 9)/4
(OSCCLK * 10)/4
Reserved
PLLSTS[DIVSEL] = 2
OSCCLK/2
(OSCCLK*1)/2
(OSCCLK*2)/2
(OSCCLK*3)/2
(OSCCLK*4)/2
(OSCCLK*5)/2
(OSCCLK*6)/2
(OSCCLK*7)/2
(OSCCLK*8)/2
(OSCCLK*9)/2
(OSCCLK*10)/2
Reserved
PLLSTS[DIVSEL] = 3
OSCCLK
OSCCLK*1
OSCCLK*2
OSCCLK*3
OSCCLK*4
OSCCLK*5
OSCCLK*6
OSCCLK*7
OSCCLK*8
OSCCLK*9
OSCCLK*10
Reserved
(1)
PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set only to 2 or 3 after PLLSTS[PLLLOCKS] = 1. By default,
PLLSTS[DIVSEL] is configured for /4. The boot ROM changes this to /2.
The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
(2)
Table 3-17. CLKIN Divide Options
PLLSTS [DIVSEL]
0
1
2
3
CLKIN DIVIDE
/4
/4
/2
/1
The PLL-based clock module provides two modes of operation:
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-18. Possible PLL Configuration Modes
CLKIN AND
SYSCLKOUT
PLL MODE
REMARKS
PLLSTS[DIVSEL]
(1)
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Off
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
0, 1
2
3
OSCCLK*n/4
OSCCLK*n/2
OSCCLK*n/1
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
PLL Enable
(1)
PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must only be set to 1 after PLLSTS[PLLLOCKS] = 1. See the
TMS320F2833x Digital Signal Controller (DSC) System Control and Interrupts Reference Guide
(literature Number
SPRUFB0
) for more
information.
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Functional Overview
57
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