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參數(shù)資料
| 型號(hào)： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 94/184頁 |
| 文件大小： | 5590K |
| 代理商： | OR3LP26B |
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94
LLucent Technologies Inc.
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description
Quad Port
(continued)
Master (FPGA Initiated) Read
Operation Setup
In order to initiate a PCI Master read operation, the
FPGA application must supply the required information
in the specific order prescribed in Table 38. The com-
mand word, burst length (if supplied), and address
must be accompanied by assertion of the enable
maenn
. The definition of the Master command word
was previously described in Table 25. The FPGA appli-
cation can use the value returned on bus
mstatecntr
,
the Master state counter’s present value, to determine
the counter’s next state, using the state diagram for the
particular operation being executed. The counter’s next
state must be determined because the FPGA applica-
tion must supply the data to the PCI core that corre-
sponds to the counter value being sent from the core to
the FPGA.
Data Transfer
The FPGA application begins receiving the read data
by deasserting
maenn
and asserting
mrdataenn
. On
every cycle that
mrdataenn
is asserted, the PCI core
clocks data from the Master read FIFO (64 deep by
36 bits wide in 32-bit PCI mode; 32 deep by 72 bits
wide in 64-bit PCI mode) to the FPGA application via
bus
mrdata
.
FIFO Empty/Almost Empty
When the Master read FIFO contains four or fewer data
elements, the PCI core asserts
mr_aemptyn
, the
almost empty indicator. This allows some latency to
exist in the FPGA’s response without risking overread-
ing the FIFO. When all locations in the Master write
FIFO are empty, the PCI core asserts
mr_empty
, the
FIFO empty indicator. Since data can be simulta-
neously written to and read from the Master read FIFO,
both
mr_aemptyn
and
mr_emptyn
can change states
in either direction multiple times in the course of a burst
data transfer.
FIFO Full
In addition to the empty and almost empty signals that
report when the Master read FIFO is currently unable
to supply data to the FPGA application, the PCI core
also provides the FIFO's full signal. During a master
read burst transaction, the master read FIFO may go
full, especially if the user side application is slow at
unloading the FIFO. When this condition occurs, the
master will insert wait-states continuously until another
word is read from the FIFO, or the word count is
exhausted. On the target side, if the target is ready to
send more data, it will have
trdyn
asserted which will
disable it from terminating the transaction as well. This
can create a deadlock condition on the PCI bus. If the
user application cannot unload any more data, and
wishes to terminate the burst, additional FPGA logic
must be incorporated to detect and accomplish the ter-
mination. Two operations must occur to terminate the
current transaction. First, the
fpga_mstopburstn
sig-
nal must be asserted indicating to the core the master
request to terminate. Second, one additional word of
data must be read from the FIFO (only if the FIFO is
full). The signal
fpga_mstopburstn
needs to stay
asserted low until the
ma_fulln
flag is asserted low
indicating that the transaction has been terminated and
cleared.
Designing a Deadlock Timer
This design example is a method by which the user
application can detect this condition and terminate the
burst transaction. Since the
mr_fulln
and
fpga_mstopburstn
signals are on the
pciclk
clock
domain, the deadlock counter will run on the
pciclk
clock. The
mr_fulln
signal is fed as a clock enable and
a synchronous clear to a counter, driven by
pciclk
. The
counter's length may be designed to guarantee a cer-
tain time-out latency on the PCI bus. When the FIFO is
not full (
mr_fulln
= 1), the counter will stay cleared.
When the FIFO has been full for an extended period of
time, the counter will count and eventually overflow.
This overflow indication can be used to set the
fpga_mstopburstn
signal indicating a request to stop
the burst. The overflow signal is then detected and syn-
chronized onto the
fclk
domain to be used to read one
additional word from the FIFO. The transaction will
complete, and the core will go back into an idle state.
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