參數(shù)資料
型號： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口
文件頁數(shù)： 89/184頁
文件大小： 5590K
代理商： OR3LP26B
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Lucent Technologies Inc.
Lucent Technologies Inc.
89
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Quad Port
(continued)
Designing a Deadlock Timer
This design example is a method by which the user
application can detect the deadlock condition and ter-
minate the burst transaction. Since the
mw_emptyn
signal is on the
pciclk
clock domain, it must be resyn-
chronized to the fclk domain. To accomplish this, dou-
ble register
mw_emptyn
with
fclk
driven registers. The
mw_emptyn
signal is fed as a clock enable and a syn-
chronous clear to a counter, driven by
fclk
. The
counter's length may be designed to guarantee a cer-
tain time-out latency on the PCI bus. When the FIFO is
not empty (
mw_emptyn
= 1), the counter will stay
cleared. When the FIFO has been empty for an
extended period of time, the counter will count and
eventually overflow. This overflow indication can be
used to write one dummy word into the FIFO with the
byte enables disabled along with the
mwlastcycn
bit
asserted. The transaction will complete, and the core
will go back into an idle state.
Bursting
Instead of using a burst length, the Master write opera-
tion relies on
mwlastcycn
to inform the PCI core on a
cycle-by-cycle basis when additional burst data is to
follow. This allows the FPGA application to maintain
control over the length of the Master write burst for as
long as possible, but may require the FPGA application
to implement a burst length counter if needed. When
executing a burst Master write, a deasserted
mwlast-
cycn
must accompany every data element except the
last element on bus
mwdata
. The signal
mwlastcycn
must remain asserted throughout a nonburst Master
write, since the last data phase is the only data phase.
The maximum burst length is limited only by the latency
timer. To initiate a burst, the starting address must be
aligned to a 64-byte boundary. If
ad[2]
is a 1, a single
transfer will be executed.
Termination
Once initiated, Master write operations will repeat on
the PCI bus until one of the following occurs:
1. All data is sent.
2. An abort occurs (either Master or Target).
3. The PCI bus’s reset signal (
rstn
) is asserted.
If a PCI transaction is terminated with a retry or discon-
nect before all data has been written, the PCI core will
initiate another Master write operation, continuing from
that point.
Reset
The FPGA application can apply the PCI core’s reset
signal
mfifoclrn
to place the core’s master logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The
mfifoclrn
signal is synchronous with
fclk
and must
be asserted for a minimum of three clock periods. Dur-
ing reset, the
m_ready
signal will go low. After the
reset signal is deasserted high,
m_ready
will continue
to be low for 8—10 clock periods. The FPGA applica-
tion should not continue normal operation until
m_ready
is asserted high.
Understanding and Using the pci_mcfg_stat Status
Signals
On the Master interface, there are two signals that con-
trol and provide status to the FPGA application. The
signal
pci_mcfg_stat
provides the status, and
mcfg-
shiftenn
controls what information the status line pro-
vides. The
pci_mcfg_stat
signal is always active and
duplicates the status contained in configuration status
register at location offset 0x04, bits 24, 28, and 29. To
use this status output, the FPGA application must keep
mcfgshiftenn
= 1. When high,
pci_mcfg_stat
pro-
vides the wired-OR of the three status lines. If
pci_mcfg_stat
gets set to a 1, indicating an error, then
the FPGA application may set
mcfgshiftenn
= 0 to
determine individual status. Once low, the
pci_mcfg_stat
signal will output data parity error
detected on the first clock, target abort on received the
second clock, and master abort received on the third
clock.
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