參數(shù)資料
型號(hào)： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 71/184頁(yè)
文件大小： 5590K
代理商： OR3LP26B
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Lucent Technologies Inc.
Lucent Technologies Inc.
71
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Quad Port
(continued)
Table 23. Embedded Core/FPGA Interface Signals
(continued)
Symbol
m_ready
I/O
Description
I
Master Logic Ready.
This active-high signal indicates that the Master logic
interfacing to the FPGA logic is ready. This signal will be inactive during PCI bus
reset or Master FIFO clears.
This signal is synchronous to
fclk
.
Master Command Code.
Command code for the current Master read/write
operation. Refer to Table 25 on page 79.
This signal must be synchronous to
fclk
.
Master Write Data FIFO Signals
mwdataenn
O
Master Write FIFO Data Enable.
This active-low signal enables the registering
of bus
datafmfpga
during Master write operations into the PCI core Master
write data FIFOs on the rising edge of the Master FIFO clock signal. The signal
mwdataenn
should not be asserted when the Master write data FIFOs are full,
or data may be lost.
This signal must be synchronous to
fclk
.
mwpcihold
O
Master Write PCI Bus Hold.
During burst transfers on the PCI bus, this signal
delays the start of the transfer on the PCI bus, allowing the FPGA application to
fill the FIFO. The transaction will begin when
mwpcihold
is deasserted or the
FIFO becomes full. When asserted,
mwpcihold
must be held low for a mini-
mum of two
pciclk
periods.
This signal must be synchronous to
pciclk
.
mw_fulln
I
Master Write Data FIFO Full Flag.
This active-low signal indicates that the
Master write data FIFOs are full.
This signal is synchronous to
fclk
.
mw_afulln
I
Master Write Data FIFO Almost Full Flag.
This active-low signal indicates that
only four more empty locations remain in the Master write data FIFOs.
This signal is synchronous to
fclk
.
mw_emptyn
I
Master Write Data FIFO Empty Flag.
This active-low signal indicates that the
Master write data FIFO is empty. Refer to Master write description on signal
usage.
This signal is synchronous to
pciclk
.
mwlastcycn
O
Master Write Last Data Cycle.
This active-low signal has two functions:
a.
It is asserted low to indicate that the accompanying 32/64 bits of Master read
or write address information is the final portion being sent. It can also be
asserted prior to any address portion being sent, indicating that the previous
address is to be used.
b.
It is asserted low to indicate that the accompanying master write data is the
final data for this operation. When more than one cycle is required to transfer
a complete data word, this signal is only valid on the last cycle.
This signal must be synchronous to
fclk
.
Master Read Data FIFO Signals
mrdataenn
O
Master Read FIFO Data Output Enable.
This active-low signal enables the
data from the PCI core Master read data FIFOs onto bus
datatofpga
during
Master read operations on the rising edge of the Master FIFO clock signal. Valid
data will be read from the FIFO whenever it is not empty.
This signal must be synchronous to
fclk
.
mr_emptyn
I
Master Read Data FIFO Empty.
This active-low signal indicates that the Mas-
ter read data FIFOs of the PCI core are empty.
This signal is synchronous to
fclk
.
mcmd[3:0]
O
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OR3LP26BBA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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