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| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 2/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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Table of Contents
Contents
Page
Contents
Page
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
2
Lucent Technologies Inc.
Introduction ..........................................................................1
PCI Bus Core Highlights ......................................................1
Figures .................................................................................2
Tables ..................................................................................3
FPSC Highlights ...................................................................5
Software Support .................................................................6
Description ...........................................................................7
What Is an FPSC ............................................................7
FPSC Overview .................................................................7
FPSC Gate Counting ........................................................7
FPGA/Embedded Core Interface ......................................7
ORCAFoundry Development System ..............................7
FPSC Design Kit ...............................................................8
FPGA Logic Overview .......................................................8
PLC Logic ..........................................................................8
PIC Logic ...........................................................................9
System Features ...............................................................9
Routing ..............................................................................9
Configuration .....................................................................9
Boundary Scan ..................................................................9
More Series 3 Information .................................................9
OR3LP26B Overview .........................................................10
Device Layout .................................................................10
PCI Local Bus .................................................................10
OR3LP26B PCI Bus Core Overview ...............................12
PCI Bus Interface ............................................................12
Embedded Core Options/FPGA Configuration ...............13
PCI Bus Core Detailed Description ....................................14
PCI Bus Commands ........................................................14
PCI Protocol Fundamentals ............................................16
FIFO Memories and Control ............................................17
PCI Bus Pin Information ..................................................18
PCI Bus Core Detailed Description Dual Port ....................21
Embedded Core/FPGA Interface Signal Descriptions ....21
Embedded Core/FPGA Interface Signal Locations .........27
Embedded Core Bit Stream Configurable Options .........32
Understanding FIFO Packing/Unpacking ........................33
Embedded Core/FPGA Interface Operation ...................34
Embedded Core/FPGA Interface Operation Summary ...35
Master (FPGA Initiated) Write .........................................36
Master (FPGA Initiated) Read .........................................42
Target (PCI Bus Initiated) Write ......................................49
Target (PCI Bus Initiated) Read ......................................58
PCI Bus Core Detailed Description Quad Port ...................70
Embedded Core/FPGA Interface Signal Descriptions ....70
Embedded Core/FPGA Interface Signal Locations .........76
Embedded Core Bit Stream Configurable Options .........83
Understanding FIFO Packing/Unpacking ........................84
Embedded Core/FPGA Interface Operation ...................86
Embedded Core/FPGA Interface Operation Summary ...87
Master (FPGA Initiated) Write .........................................88
Master (FPGA Initiated) Read .........................................94
Target (PCI Bus Initiated) Write ....................................101
Target (PCI Bus Initiated) Read ....................................110
Configuration Space of the PCI Core ...............................123
PCI Bus Configuration Space Organization ..................123
FPSC Configuration ......................................................... 126
Configuration via PCI Bus ............................................. 126
Readback via PCI interface .......................................... 127
Interaction Among Configuration Modes ......................127
Clocking Options at FPGA/Core Boundary ..................... 128
PCI Clock as System Clock .......................................... 128
Local Clock as System Clock .......................................128
FPGA Configuration Data Format ................................... 130
Using ORCAFoundry to Generate Configuration
RAM Data ...................................................................130
FPGA Configuration Data Frame .................................. 130
Bit Stream Error Checking ............................................... 132
FPGA Configuration Modes ............................................. 132
Powerup Sequencing for Series OR3LP26B Device ....... 133
Absolute Maximum Ratings ............................................. 133
Recommended Operating Conditions ............................. 134
Electrical Characteristics ................................................. 135
Timing Characteristics ..................................................... 136
Description .................................................................... 136
Clock Timing ................................................................. 137
Input/Output Buffer Measurement Conditions ................. 148
Output Buffer Characteristics .......................................... 149
Estimating Power Dissipation .......................................... 150
Pin Information ................................................................ 151
Package Compatibility ..................................................154
Package Thermal Characteristics Summary ................... 178
Θ
JA ............................................................................... 178
ψ
JC ............................................................................... 178
Θ
JC ............................................................................... 178
Θ
JB ............................................................................... 178
FPGA Maximum Junction Temperature ....................... 178
Package Coplanarity ....................................................... 179
Package Parasitics .......................................................... 180
Package Outline Diagrams .............................................. 181
Terms and Definitions ................................................... 181
352-Pin PBGA .............................................................. 182
680-Pin PBGA .............................................................. 183
Ordering Information ........................................................184
Figures
Figure 1. ORCA OR3LP26B PCI FPSC
Block Diagram...............................................................13
Figure 2. Master Write Single (FPGA Bus, Dual-Port).....38
Figure 3. Master Write Single (PCI Bus, 64-Bit)..............39
Figure 4. Master Write 32-Byte Burst
(FPGA Bus, Dual-Port) .................................................40
Figure 5. Master Write 32-Byte Burst (PCI Bus, 64-Bit) ..41
Figure 6. Master Read Single (FPGA Bus, Dual-Port,
Specified Burst Length, 64-Bit Address).......................44
Figure 7. Master Read Single (PCI Bus, 64-Bit)..............45
Figure 8. Master Read 32-Byte Burst (FPGA Bus,
Dual-Port, Burst Length, and 64-Bit Address) ..............46
Figure 9. Master Read 32-Byte Burst
(PCI Bus, 64-Bit)...........................................................47
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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