- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384756 > MT49H32M9C (Micron Technology, Inc.) 288Mb SIO REDUCED LATENCY(RLDRAM II) PDF資料下載
參數(shù)資料
| 型號(hào)： | MT49H32M9C |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 288Mb SIO REDUCED LATENCY(RLDRAM II) |
| 中文描述： | 288Mb二氧化硅約化延遲（延遲DRAM二） |
| 文件頁(yè)數(shù)： | 33/44頁(yè) |
| 文件大?。?/td> | 1117K |
| 代理商： | MT49H32M9C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)當(dāng)前第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
33
Configuration Table
In this mode, the READ and WRITE latencies are
increased by one clock cycle. The RLDRAM cycle time
remains the same, as described in Table 11.
NOTE:
1. BL = 8 is not available for configuration 1.
Refresh Command in Multiplexed
Address Mode
Similar to other commands, the refresh command is
executed on the next rising clock edge when in the
multiplexed address mode. However, since only bank
address is required for AREF, the next command can be
applied on the following clock. The operation of the
AREF command and any other command is repre-
sented in Figure 35.
Figure 35: Burst Refresh Operation
NOTE:
AREF: AUTO REFRESH
AC: Any command
A
x
: First part A
x
of address
A
y
: Second part A
y
of address
BA
k
: Bank
k
;
k
is chosen so that
t
RC is met
Table 11:
Configuration Table In Multiplexed Address Mode
CONFIGURATION
FREQUENCY
SYMBOL
1
1
4
2
6
3
8
UNIT
cycles
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
t
RC
t
RL
t
WL
5
7
9
cycles
6
8
10
cycles
400 MHz
20.0
ns
22.5
ns
25.0
ns
300 MHz
20.0
26.7
ns
23.3
30.0
ns
26.7
33.3
ns
200 MHz
20.0
30.0
40.0
ns
25.0
35.0
45.0
ns
35.0
40.0
50.0
ns
ADDR
CK#
CK
CMD
0
1
2
3
4
5
6
7
8
AC
AREF
AREF
AREF
AREF
AREF
AREF
AREF
DON’T CARE
AREF
9
10
Ax
Ay
AC
Ax
Ay
11
BADDR
BAk
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BAk
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT49H32M9CFM-xx | 288Mb SIO REDUCED LATENCY(RLDRAM II) |
| MT4C1004J | 4 Meg x 1 FPM DRAM(4 M x 1快速頁(yè)面模式動(dòng)態(tài)RAM) |
| MT4C4001STG-6 | standard or self refresh |
| MT4C4001STG-7 | standard or self refresh |
| MT4C4001STG-8 | standard or self refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT49H32M9CFM-25 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Trays |
| MT49H32M9CFM-33 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Trays |
| MT49H32M9CFM-5 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Tape and Reel |
| MT49H32M9CFM-XX | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:288Mb SIO REDUCED LATENCY(RLDRAM II) |
| MT49H32M9CHU-25 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。