參數(shù)資料
型號(hào): MT49H32M9C
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁(yè)數(shù): 30/44頁(yè)
文件大?。?/td> 1117K
代理商: MT49H32M9C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
30
Operation with Multiplexed Addresses
In multiplexed address mode, the address can be
provided to the RLDRAM in two parts that are latched
into the memory with two consecutive rising clock
edges. This provides the advantage that a maximum SP
of 11 address balls are required to control the
RLDRAM, reducing the number of balls on the control-
ler side. The bank addresses are delivered to the
RLDRAM at the same time as the write command and
the first address part, Ax.
This option is available by setting bit A5 to “1” in the
mode register. Once this bit is set, the READ, WRITE,
and MRS commands follow the format described in
Figure 32. See Figure 34 on page 31 for the power-up
sequence.
Figure 32: Command Description in Multiplexed Address Mode
NOTE:
1. Ax, Ay: Address
BA: Bank Address
2. The minimum setup and hold times of the two address parts are defined
t
AS and
t
AH.
CK#
CK
WE#
REF#
CS#
Ax
BA
A<20:0>
BA<2:0>
READ
Ay
Ax
BA
WRITE
Ay
Ax
BA
DON’T CARE
MRS
Ay
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