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| 型號(hào)： | MT49H32M9C |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 288Mb SIO REDUCED LATENCY(RLDRAM II) |
| 中文描述： | 288Mb二氧化硅約化延遲（延遲DRAM二） |
| 文件頁(yè)數(shù)： | 21/44頁(yè) |
| 文件大?。?/td> | 1117K |
| 代理商： | MT49H32M9C |
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16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
21
Read Basic Information
Read accesses are initiated with a READ command,
as shown in Figure 17. Row and bank addresses are
provided with the READ command.
During READ bursts, the memory device drives the
read data edge-aligned with the QK signal. After a pro-
grammable read latency, data is available at the out-
puts. The data valid signal indicates that valid data will
be present in the next half clock cycle.
The skew between QK and the crossing point of CK
is specified as
t
CKQK.
t
QKQ0 is the skew between QK0
and the last valid data edge considered over all the
data generated at the Q signals.
t
QKQ1 is the skew
between QK1 and the last valid data edge considered
over all the data generated at the Q signals.
t
QKQx is
derived at each QKx clock edge and is not cumulative
over time.
t
QKQ is the maximum of
t
QKQ0 and
t
QKQ1.
After completion of a burst, assuming no other
commands have been initiated, output data (Q) will go
High-Z. Back-to-back READ commands are possible,
producing a continuous flow of output data.
The data valid window is derived from each QK
transition and is defined as:
MIN (
t
QKH,
t
QKL) - 2(
t
QKQ [MAX]).
Any READ burst may be followed by a subsequent
WRITE command. Figures 21 and 22 illustrate the tim-
ing requirements for a READ followed by a WRITE.
Figure 17: READ Command
NOTE:
A: address; BA: bank address.
CK#
CK
WE#
REF#
CS#
A
BA
A(20:0)
BA(2:0)
DON’T CARE
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PDF描述 |
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| MT49H32M9CFM-xx | 288Mb SIO REDUCED LATENCY(RLDRAM II) |
| MT4C1004J | 4 Meg x 1 FPM DRAM(4 M x 1快速頁(yè)面模式動(dòng)態(tài)RAM) |
| MT4C4001STG-6 | standard or self refresh |
| MT4C4001STG-7 | standard or self refresh |
| MT4C4001STG-8 | standard or self refresh |
相關(guān)代理商/技術(shù)參數(shù) |
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| MT49H32M9CFM-25 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Trays |
| MT49H32M9CFM-33 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Trays |
| MT49H32M9CFM-5 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Tape and Reel |
| MT49H32M9CFM-XX | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:288Mb SIO REDUCED LATENCY(RLDRAM II) |
| MT49H32M9CHU-25 | 制造商:Micron Technology Inc 功能描述:DRAM CHIP RLDRAM 288MBIT 1.8V 144FBGA - Trays |
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