參數(shù)資料
型號(hào): MT49H32M9C
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁數(shù): 27/44頁
文件大?。?/td> 1117K
代理商: MT49H32M9C
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
27
AUTO REFRESH Command (AREF)
AREF is used to perform a refresh cycle on one row
in a specific bank. The row addresses are generated by
an internal refresh counter for each bank; external
address balls are “Don’t Care.” The delay between the
AREF command and a subsequent command to the
same bank must be at least
t
RC.
Within a period of 32ms (
t
REF), the entire memory
must be refreshed. Figure 27 illustrates an example of a
continuous refresh sequence. Other refresh strategies,
such as burst refresh, are also possible.
Figure 26: AUTO REFRESH Command
NOTE:
BA: Bank address.
Figure 27: AUTO REFRESH Cycle
NOTE:
1. AC
x
: Any command on bank
x
ARF
x
: Auto Refresh bank
x
ACy: Any command on different bank
2.
t
RC is configuration-dependent. Refer to Table 8, RLDRAM Configuration Table, on page 17.
CK#
CK
WE#
REF#
CS#
BA
A(20:0)
BA(2:0)
CK#
CK
CMD
t
RC
ARF
x
AC
y
AC
x
AC
y
ARF
x
AC
y
DON’T CARE
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