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參數(shù)資料
| 型號(hào)： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁數(shù)： | 95/164頁 |
| 文件大?。?/td> | 1072K |
| 代理商： | MC145574 |
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MC145574
10–5
MOTOROLA
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR7
Disable
3 V
Regulator
Enable
S/G Bit
Enable
TCLK
Dual Frame
Syncs
Long
Frame
8/10 Bit
Select
TSEN B1/B2
Enable,
BCL Enable
TSEN
D Channel
Enable
OR7(7) — Control Register, Disable 3 V Regulator
This bit can be used to disable the supply regulator and allow three volts to be driven from an external
supply. This bit is reset to a logic 0 by RESET and software reset.
OR7(6) — Enable S/G Bit
This bit can be enabled only in GCI 1.536 MHz clock mode. This bit provides the availability of the
D channel on the S/T loop. 1 = Stop (no availability of the D channel), and 0 = Go (availability of the
D channel). Refer to Section 11.2.5.
OR7(5) — Control Register, Enable TCLK
This is available in TE IDL2 slave mode to enable TCLK instead of TFSC. Both TFSC and TCLK
are synchronized to the received S/T frames and can be used as a source of network synchronization
for the slave device. Refer to the section on slave–slave mode for further details.
OR7(4) — Control Register, Dual Frame Syncs
This bit controls whether the IDL2 operates with one– or two–frame syncs. When set to a logic 0,
the device operates with one–frame sync, and the FSC is the sync for both the Tx and Rx directions.
When this bit is set to a logic 1, the FST pin is activated to be the Tx frame sync, and the FSC pin
becomes the FSR (Rx frame sync). These pins will be either an input or an output depending on whether
the IDL2 is a master or a slave. This bit is only functional in IDL2 mode. If dual frame syncs are enabled,
then TSEN cannot be enabled.
OR7(3) — Control Register, Long Frame
This bit controls whether the FSC operates in long or short frame mode, while operating as an IDL2
master. If this bit is set to a 1, then the IDL2 is in long frame mode. As an IDL2 slave, the MC145574
determines the mode, based on the length of the FS. The length of the long frame is eight bit clocks,
regardless of whether 8– or 10–bit format is selected. The long frame sync cannot be used in conjunc-
tion with timeslot assignment.
OR7(2) — Control Register, 8/10 Bit Select
When the device is initialized, this bit is a logic 0. When set to a logic 0, the IDL2 will use the 10–bit
format. When set to a logic 1, the IDL2 will use the 8–bit format. When IDL2 timeslot assigner mode
is enabled, the 8–bit mode is set and this bit has no effect.
OR7(1) — Control Register, TSEN B1/B2 Enable (IDL2), BCL Enable (GCI)
After any reset, this bit is a 0. This bit controls the operation of the TSEN/BCL pin.
IDL2: TSEN B1/B2 Enable. When this bit is set to a 1, the TSEN pin function is enabled during the
B1 and B2 bit times. The signal goes low when B1 or B2 data is present on Dout. This signal can
be used to control a bus or backplane driver. Dual frame syncs cannot be enabled when this bit is
set to a 1.
GCI: BCL Enable. When this bit is set to a 1, the BCL pin function (the 1/2 DCL clock rate signal)
is enabled. Dual frame syncs cannot be enabled when this bit is set to a 1.
OR7(0) — Control Register, TSEN D Channel Enable
When the device is initialized, this bit is logic 0. When set to a logic 1, the TSEN signal goes low
when D channel data is being output on Dout. This bit is only functional in IDL2 mode. If TSEN is
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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