參數(shù)資料
型號： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù)： 52/164頁
文件大?。?/td> 1072K
代理商： MC145574
MC145574
6–6
MOTOROLA
The alternative GCI mode is direct mode. This mode should be used when a fully–compliant GCI
is required. In this mode, the SCP interface is not available.
In a GCI direct mode the monitor, C/I, and A/E channels are fully active and compatible with the GCI
standards.
To enter a GCI direct mode, the SCPEN/GCIEN pin should be tied to VSS and a reset applied to the
device. The GCI direct mode is selected on the rising edge of RESET. The GCIEN pin must be tied
to VSS at all times when GCI direct mode is the required mode of operation. The GCIEN pin is continu-
ously sampled internally. A “zero–to–one” transition on GCIEN will cause the MC145574 to exit from
a GCI direct mode into IDL/SCP mode.
In GCI direct mode, the IRQ function is not required and is internally disabled.
On entering GCI direct mode, the pins of the MC145574 are redefined as follows.
SCPEN changes to GCIEN (an input).
FST changes to BCL (an output).
SCPCLK changes to S2 (an input) in slave mode, and M2 (an input) in master mode.
SCP Rx changes to S1 (an input) in slave mode, and M1 (an input) in master mode.
SCP Tx changes to S0 (an input) in slave mode, and M0 (an input) in master mode.
DGRANT changes to SG (an output) in TE master mode.
BCL is enabled in both the slave and master mode. BCL is an output clock which is the DCL
clock divided by two. BCL is synchronous with FSC and can be used by non–GCI devices which
require a locked bit frequency clock to access the B and D channel slots (i.e., codec).
In the slave mode, DCL and FSC are inputs. DCL can be any frequency between 512 kHz and
4.096 MHz. In the slave mode, S2, S1, and S0 pins control the timeslot in which the device operates.
In the NT slave mode, it is possible to select both NT1 Star and NT Terminal modes via the Monitor
channel. The associated pins used in the default IDL2 mode are enabled and operate in the same
manner.
In the TE slave mode, the TFSC/TCLK pin is enabled and it is possible to select the TCLK and its
frequency via the Monitor channel.
In the master mode, DCL and FSC are outputs. The M2, M1, and M0 pins control mode selection
in master mode; however, these modes are defined differently for the NT and TE master.
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For More Information On This Product,
Go to: www.freescale.com
Table 6–3. M2, M1, and M0 Pins in GCI NT Master Mode
M2
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0
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0
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0
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0
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1
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1
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1
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1
M1
M0
GCI NT Master Mode
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DCL = 2.048 MHz, Channel 0
DCL = 2.048 MHz, Channel 1
DCL = 2.048 MHz, Channel 2
DCL = 2.048 MHz, Channel 3
DCL = 1.536 MHz, Channel 0
DCL = 1.536 MHz, Channel 1
DCL = 1.536 MHz, Channel 2
DCL = 512 kHz, Channel 0
F
Freescale Semiconductor, Inc.
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