參數(shù)資料
型號(hào)： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù)： 108/164頁
文件大?。?/td> 1072K
代理商： MC145574
MC145574
13–2
MOTOROLA
In slave mode, the IDL2/GCI interface frame sync and clock are inputs, and the S/T loop interface
timing is slaved to these inputs. In master mode, the IDL2/GCI interface frame sync and clock are
outputs; these signals being derived from the 15.36 MHz XTAL oscillator. The S/T loop interface timing,
however, is always slaved to the IDL2/GCI frame sync.
Therefore, in NT mode, the S/T loop interface timing is always slaved to the IDL2/GCI frame sync.
The source of this timing can be selected to be from the IDL2/GCI driver (slave mode) or from the
NT device itself (master mode).
NT master mode will be referred to as NTM, and NT slave mode as NTS.
It is also possible to select NTM by writing to the SCP control bit BR7(3). Or alternatively in TE or
NT mode, master selection can be made via OR8(3). The master/slave pin is internally OR’d with
these SCP bits and should be held low if register is to be used.
In NT mode, two further mode extensions can be selected via control bits accessible through the SCP.
These NT mode extensions have no effect on the IDL2 interface, but alter the operation of other pins
to perform the desired functions. These two modes are called NT1 Star and NT Terminal.
Table 13–1. Pin Operations
Pin
NT
NT1 Star
NT Terminal
TQFP Pin 3
SOIC Pin 6
FIX
FIX
T_IN
TQFP Pin 5
SOIC Pin 8
High–Z
ANDOUT
DGRANT
TQFP Pin 6
SOIC Pin 9
Tie–Low
ANDIN
DREQUEST
TQFP Pin 7
SOIC Pin 10
Tie–Low
ECHO IN
CLASS
Appendix B of ANSI T1.605 describes an example of an NT that will support multiple T interfaces.
This is to accommodate multipoint operation with more than eight TEs. The MC145574 can be config-
ured for NT1 Star mode of operation. This mode is for use in wire OR’ing multiple NT–configured
S/T chips on the IDL2 side. Each NT has a common FSC, DCL, Dout, and Din, as shown in Figure
13–2. Each NT is then connected to its own individual S/T loop containing either a single TE or a
group of TEs. As such, the contention for either of the B channels or for the D channel is now extended
from a single passive bus to a grouping of passive busses.
ISDN employs the use of HDLC data on the D channel. Access to either of the B channels is requested
and either granted or denied by the user sending layer 2 frames on the D channel. In normal operation
where there is only one NT, the TEs are granted access to the D channel in accordance with their
priority and class. By counting the required number of E channel echo bits being 1, the TEs know
when the D channel is clear. Thus, in the NT1 Star mode of operation, where there are multiple passive
busses competing for the same B1, B2, and D channels, the same E echo channel must be transmitted
from each NT to its passive bus. This is accomplished in the MC145574 by means of the ANDIN,
ANDOUT, and ECHO IN pins.
Figure 13–2 shows how to connect the multiple number of NTs in the NT1 Star mode. Successive
connection of the ANDOUT (this is the output of an internal AND gate whose inputs are the demodu-
lated D bits and the data on the ANDIN pin) and ANDIN pins, and the common connections of the
ECHO IN pins, succeeds in sending the same E echo channel to each group of TE(s). To configure
a series of NTs for NT1 Star mode, BR13(7) must be set to 1 in each NT. Data transmitted on Tx
in NT1 Star mode will have the following format: a logic 0 is VSS; a logic 1 causes Dout to go to a
high–impedance state. This then permits the series wire OR’ing of the IDL2 bus. Note that one of
the NTs must have its ANDIN pin pulled high.
NT1 Star mode is not applicable to the NT using the GCI interface.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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