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參數(shù)資料
| 型號(hào)： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁(yè)數(shù)： | 45/164頁(yè) |
| 文件大?。?/td> | 1072K |
| 代理商： | MC145574 |
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MC145574
5–7
MOTOROLA
This signal, when held low, selects the SCP for the transfer of control, status, and data information
into and out of the MC145574 S/T transceiver. SCPEN should be held low for 8 or 16 periods of the
SCPCLK signal, in order for information to be transferred into or out of the MC145574 S/T transceiver.
The phase relationship of SCPEN, with respect to SCPCLK, is as shown in Figures 5–1 through 5–6
inclusive.
The transition of SCPEN going high will abort any SCP operation in progress, and will force the SCP Tx
pin into the high–impedance state.
IRQ is an open drain output to the device used for indicating that an interrupt condition exists. This
pin is normally pulled high by an external resistor. When this pin goes low, it indicates a read operation
of the interrupt status register (NR3) is required.
The MC145574 S/T transceiver has the capability of forcing all output pins of the MC145574 (both
analog and digital) to the high–impedance state. This feature, known as the “Serial Control Port High–
Impedance Digital Output Mode”, or SCP HIDOM, is provided to allow “in circuit” testing of other circuits
or devices resident on the same PCB, without requiring the removal of the MC145574.
The SCP HIDOM mode is entered by holding SCPEN low for a minimum of 33 consecutive rising
edges of SCPCLK while SCP Rx is high. After entering this mode, if SCPEN goes high or if SCP Rx
goes low, the device will exit the SCP HIDOM mode and return to normal operation.
!#!!& " $(%&
The MC145574 S/T transceiver operates with a 15.36 MHz crystal frequency. Details of the crystal
circuit can be found in Section 7. The SCP operates independently of the 15.36 MHz crystal; i.e.,
the SCP can be accessed in the presence or absence of the 15.36 MHz input.
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The SCP in the MC145574 always operates in the SCP slave mode. The SCP slave mode is defined
as having SCPCLK and SCPEN as inputs to the device. Thus, any device which communicates with
the MC145574 via the SCP must be able to operate in the SCP master mode where SCPCLK and
SCPEN are outputs. Note that the MC145488 dual data link controller (DDLC) and 68302 operate
in the SCP master mode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC145574AEG | 制造商:Freescale Semiconductor 功能描述: |
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