參數(shù)資料
型號(hào)： MAX1359BCTL-T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
文件頁(yè)數(shù)： 73/74頁(yè)
文件大?。?/td> 1214K
代理商： MAX1359BCTL-T
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
8
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, CLK32K = 32.768kHz (external clock), CREG = 10F, CCPOUT =
10F, 10F between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25
°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DVDD Monitor Turn-On Time
5ms
CPOUT Monitor Supply Voltage
Range
1.0
3.6
V
CPOUT Monitor Trip Threshold
2.7
2.8
2.9
V
CPOUT Monitor Hysteresis
35
mV
CPOUT Monitor Turn-On Time
5ms
Internal Power-On Reset Voltage
1.7
V
32kHz Oscillator (32KIN, 32KOUT)
Clock Frequency
DVDD = 2.7V
32.768
kHz
Stability
DVDD = 1.8V to 3.6V, excluding crystal
25
ppm
Oscillator Startup Time
1500
ms
Crystal Load Capacitance
6pF
LOW-FREQUENCY CLOCK INPUT/OUTPUT (CLK32K)
Output Clock Frequency
32.768
kHz
Absolute Input to Output Clock
Jitter
Cycle to cycle
5
ns
Input to Output Rise/Fall Time
10% to 90%, 30pF load
5
ns
Input/Output Duty Cycle
40
60
%
HIGH-FREQUENCY CLOCK OUTPUT (CLK)
fOUT = fFLL
4.8660
4.9152
4.9644
fOUT = fFLL / 2, power-up default
2.4330
2.4576
2.4822
fOUT = fFLL / 4
1.2165
1.2288
1.2411
MHz
FLL Output Clock Frequency
fOUT = fFLL / 8
608.25
614.4
620.54
kHz
Cycle to cycle, FLL off
0.15
Absolute Clock Jitter
Cycle to cycle, FLL on
1
ns
Rise and Fall Time
tR/tF
10% to 90%, 30pF load
10
ns
fOUT = 4.9152MHz
40
60
Duty Cycle
fOUT = 2.4576MHz, 1.2288MHz, 614.4kHz
45
55
%
Uncalibrated CLK Frequency
Error
FLL calibration not performed
±35
%
DIGITAL INPUTS (SCLK, DIN,
CS, UPIO_, CLK32K)
Input High Voltage
VIH
0.7 x
DVDD
V
Input Low Voltage
VIL
0.3 x
DVDD
V
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